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Gate mem_rd in mem_if

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This commit is contained in:
Olof Kindgren 2019-09-26 23:31:23 +02:00
parent 0f767ad2d3
commit 2b5c71fe9b
3 changed files with 4 additions and 8 deletions
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4
rtl/serv_decode.v
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@ -55,8 +55,7 @@ module serv_decode
output wire o_imm,
output wire o_op_b_source,
output wire o_rd_csr_en,
output wire o_rd_alu_en,
output wire o_rd_mem_en);
output wire o_rd_alu_en);
`include "serv_params.vh"
@ -226,7 +225,6 @@ module serv_decode
assign o_op_b_source = opcode[3];
assign o_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4];
assign o_rd_mem_en = !opcode[2] & !opcode[4];
endmodule

2
rtl/serv_mem_if.v
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@ -39,7 +39,7 @@ module serv_mem_if
(dat_sel == 1) ? dat1[0] : dat0[0];
wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]);
assign o_rd = dat_valid ? dat_cur : signbit & i_signed;
assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed);
wire upper_half = i_lsb[1];

6
rtl/serv_top.v
View File

@ -55,7 +55,6 @@ module serv_top
wire slt_op;
wire rd_alu_en;
wire rd_mem_en;
wire rd_csr_en;
wire ctrl_rd;
wire alu_rd;
@ -231,8 +230,7 @@ module serv_top
.o_imm (imm),
.o_op_b_source (op_b_source),
.o_rd_csr_en (rd_csr_en),
.o_rd_alu_en (rd_alu_en),
.o_rd_mem_en (rd_mem_en));
.o_rd_alu_en (rd_alu_en));
assign o_dbus_adr = {bufreg_out[31:2], 2'b00};
@ -284,7 +282,7 @@ module serv_top
assign rd = (ctrl_rd ) |
(rd_alu_en & alu_rd ) |
(csr_rd & rd_csr_en) |
(rd_mem_en & mem_rd);
(mem_rd);
assign op_b = (op_b_source == OP_B_SOURCE_IMM) ? imm : rs2;