17 Commits

Author	SHA1	Message	Date
Olof Kindgren	8bc54a99ad	Move mcause generation to serv_csr	2019-09-26 23:36:02 +02:00
Olof Kindgren	1248043a39	Separate state and decode from CSR signals	2019-09-14 22:18:03 +02:00
Olof Kindgren	d2cf7e547a	Interrupt refactoring	2019-08-25 22:47:29 +02:00
Olof Kindgren	16c93a58ee	Move mepc and mtval into RF memory	2019-07-08 07:49:58 +02:00
Olof Kindgren	e107627e71	Reduce warnings	2019-06-24 15:22:08 +02:00
Olof Kindgren	42ac1e5e4d	Store CSR in RF RAM ... Since FPGA uses fixed-size RAM, it's better in most cases to store the CSR in unused memory positions in that RAM. Since the decoding is made more complex, the old register file implementation is kept around since that is more efficient when we don't want CSR and potentially when the FPGA support hardware shift registers.	2019-06-07 19:39:18 +02:00
Olof Kindgren	3438e0f172	Optimize mcause CSR	2019-03-21 09:24:11 +01:00
Olof Kindgren	9a97c535bd	Use ring buffer for counter LSBs	2019-01-15 08:00:32 +01:00
Olof Kindgren	45f6d408f8	Remove dead code	2019-01-15 08:00:32 +01:00
Olof Kindgren	813f9f4951	Rewrite CSR selection	2019-01-10 18:15:20 +01:00
Olof Kindgren	468e99ac7c	Syntax fixes to please Quartus	2018-12-07 22:55:55 +01:00
Olof Kindgren	cd983190b3	Interrupts working. Adding philosophers example	2018-11-26 23:03:40 +01:00
Olof Kindgren	11a2195146	First attempt att interrupt support	2018-11-26 16:01:07 +01:00
Olof Kindgren	b8f5133267	Random optimizations	2018-11-23 13:59:07 +01:00
Olof Kindgren	f66f82a57a	Add explicit wire defs to ports	2018-11-17 21:30:03 +01:00
Olof Kindgren	0036756157	Pass compliance tests	2018-11-15 14:16:01 +01:00
Olof Kindgren	a92c933af1	csr, verilator, traps	2018-11-14 12:16:20 +01:00