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Code Issues Releases Wiki Activity
177 Commits 11 Branches 9 Tags
e2147776f25df266be41313753a0dd4bb9f0f5af
Commit Graph

9 Commits

Author SHA1 Message Date
Olof Kindgren
fca1527dd7 Add cyc1000 target 2020-02-29 15:29:07 +01:00
Olof Kindgren
e39b4770fd Add quartus-friendly RAM implementation 2020-02-29 15:26:17 +01:00
Olof Kindgren
ed02951b4d Add vcd_start parameter 2019-11-19 10:46:15 +01:00
Gwenhael Goavec-Merou
61c8a6b886 add arty_a7_35t support 2019-11-10 21:44:50 +01:00
Gwenhael Goavec-Merou
d90030b955 xilinx PLL: allows to specify PLL output frequency (16 or 32 MHz) 2019-11-10 21:44:50 +01:00
Olof Kindgren
e059b7cf09 Add timeout argument 2019-08-25 22:52:34 +02:00
Olof Kindgren
65eb89323a Replace wb_ram with servant_ram 2019-08-25 22:51:50 +02:00
Olof Kindgren
4b371c533f Add nexys a7 support 2019-06-24 13:18:34 +02:00
Olof Kindgren
cf7e516526 Refactor to separate serv and servant 2019-06-24 13:18:34 +02:00