Olof Kindgren
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3829d05786
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Add zcu106 support to servant
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2020-04-15 10:18:06 +02:00 |
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Olof Kindgren
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eff17d2f7c
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Prepare for release
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2020-03-04 22:34:46 +01:00 |
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Olof Kindgren
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c9a3c883f1
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Refactor testbench
Introduce an intermediate common simulation toplevel for verilator
and other sims
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2020-03-03 09:15:50 +01:00 |
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Olof Kindgren
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fca1527dd7
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Add cyc1000 target
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2020-02-29 15:29:07 +01:00 |
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Olof Kindgren
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e39b4770fd
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Add quartus-friendly RAM implementation
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2020-02-29 15:26:17 +01:00 |
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Olof Kindgren
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ed02951b4d
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Add vcd_start parameter
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2019-11-19 10:46:15 +01:00 |
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Gwenhael Goavec-Merou
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61c8a6b886
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add arty_a7_35t support
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2019-11-10 21:44:50 +01:00 |
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Gwenhael Goavec-Merou
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d90030b955
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xilinx PLL: allows to specify PLL output frequency (16 or 32 MHz)
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2019-11-10 21:44:50 +01:00 |
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Olof Kindgren
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e059b7cf09
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Add timeout argument
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2019-08-25 22:52:34 +02:00 |
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Olof Kindgren
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65eb89323a
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Replace wb_ram with servant_ram
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2019-08-25 22:51:50 +02:00 |
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Olof Kindgren
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4b371c533f
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Add nexys a7 support
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2019-06-24 13:18:34 +02:00 |
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Olof Kindgren
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cf7e516526
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Refactor to separate serv and servant
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2019-06-24 13:18:34 +02:00 |
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