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193 Commits 11 Branches 9 Tags
Commit Graph

7 Commits

Author SHA1 Message Date
Olof Kindgren
c9a3c883f1 Refactor testbench 
Introduce an intermediate common simulation toplevel for verilator
and other sims
 2020-03-03 09:15:50 +01:00
Olof Kindgren
ed02951b4d Add vcd_start parameter 2019-11-19 10:46:15 +01:00
Olof Kindgren
9c83e39635 Initialize state of verilator UART decoder 2019-11-04 13:01:31 +01:00
Olof Kindgren
57b4fca05f Ignore initial garbage in verilator UART decoder 2019-10-29 21:53:13 +01:00
Olof Kindgren
e059b7cf09 Add timeout argument 2019-08-25 22:52:34 +02:00
Olof Kindgren
70bdce9d8e Refactor gpio/uart output in tb 2019-06-24 13:18:34 +02:00
Olof Kindgren
cf7e516526 Refactor to separate serv and servant 2019-06-24 13:18:34 +02:00