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Author SHA1 Message Date
Olof Kindgren
4f902829a3 Bump core version serv-1.0.1 2020-04-19 23:06:54 +02:00
Olof Kindgren
fda7dd288a Optimize enable signal for mem_if buffers 2020-04-15 22:48:28 +02:00
Olof Kindgren
1d311edb7d Make counter internal in serv_state 2020-04-15 10:29:50 +02:00
Olof Kindgren
3829d05786 Add zcu106 support to servant 2020-04-15 10:18:06 +02:00
Olof Kindgren
09c7d6dbbf Remove FSM from serv_state 2020-04-05 00:22:44 +02:00
Olof Kindgren
8dd75fa752 Stop using states in logic expressions 2020-04-04 23:44:29 +02:00
Olof Kindgren
9a8dcde030 Simplify o_dbus_adr assignment 2020-04-03 22:58:24 +02:00
Olof Kindgren
4f855602fa Add serving SoClet 2020-03-27 09:08:02 +01:00
Olof Kindgren
6b0e4fb3ea Disable misalignment traps when CSR is disabled 2020-03-27 08:55:34 +01:00
Olof Kindgren
726e520cce Fix lint warnings when CSR is disabled 2020-03-25 23:32:12 +01:00
Olof Kindgren
b4a0015dc4 Fix linker script 2020-03-25 23:32:12 +01:00
dh73
2a7596b51d Declare variables/nets before referenced 2020-03-25 23:31:55 +01:00
Olof Kindgren
eff17d2f7c Prepare for release 1.0.0 v1.0 2020-03-04 22:34:46 +01:00
Olof Kindgren
3e9e25e984 Avoid resetting bufreg 2020-03-03 09:21:55 +01:00
Olof Kindgren
c9a3c883f1 Refactor testbench 
Introduce an intermediate common simulation toplevel for verilator
and other sims
 2020-03-03 09:15:50 +01:00
Olof Kindgren
3468958f1e Whitespace fixes 2020-03-02 21:20:51 +01:00
Olof Kindgren
e2147776f2 servant: Rename some wires 2020-03-02 16:29:01 +01:00
Olof Kindgren
b48b02b8df Add parameter to disable CSR/interrupts 
Also disables timer in servant if CSR/interrupts are disabled
 2020-03-02 16:17:26 +01:00
Olof Kindgren
fca1527dd7 Add cyc1000 target 2020-02-29 15:29:07 +01:00
Olof Kindgren
e39b4770fd Add quartus-friendly RAM implementation 2020-02-29 15:26:17 +01:00
Olof Kindgren
ea1936710e Inline ser_lt 2020-02-19 13:15:18 +01:00
Olof Kindgren
afb7e641dd Inline adders 2020-02-19 11:00:55 +01:00
Olof Kindgren
7f16f17ca5 Optimize CSR immediate handling 2020-02-19 10:02:48 +01:00
Olof Kindgren
badcd7ea55 Remove duplicate signals in serv_state 2020-02-17 23:48:39 +01:00
Olof Kindgren
36746d3890 Remove unused signals 2020-02-17 23:01:49 +01:00
Olof Kindgren
5aa1fbe709 Stop depending on run state 2019-12-08 22:51:28 +01:00
Olof Kindgren
6067b0e684 Use one-hot encoding for ALU rd sel 2019-12-07 23:36:36 +01:00
Olof Kindgren
eb5d25ea1c Move op_b mux to alu 2019-12-07 23:09:04 +01:00
Olof Kindgren
b516c10d72 Prepare for RF write on RF read request and optimize state FSM 2019-12-07 23:01:24 +01:00
Olof Kindgren
31c138e4a1 Create RAM and RF IF with configurable widths 2019-12-05 22:35:53 +01:00
Olof Kindgren
68d8af71f2 Use serv_rf_top in default and lint targets 2019-12-05 22:35:14 +01:00
Olof Kindgren
e93fd0d30e Fix compile errors with RISCV_FORMAL 2019-12-04 23:42:40 +01:00
Olof Kindgren
3179cfb107 Optimize alu eq_r and lt_r 2019-12-03 10:28:27 +01:00
Olof Kindgren
8b82c85fb6 Create toplevel without RF 2019-11-20 18:26:04 +01:00
Olof Kindgren
4532c8dafd Move rd selection to rf_if 2019-11-20 18:26:04 +01:00
Olof Kindgren
04037c4354 Split out RF to separate module 2019-11-20 18:26:04 +01:00
Olof Kindgren
fc348f3a22 Fix wen delays in rf 2019-11-20 18:26:04 +01:00
Olof Kindgren
a7d7d6475b Update Zephyr port to v1.14 2019-11-19 13:44:17 +01:00
Olof Kindgren
40000cbeb9 Fix IRQ 
This contains a lot of fixes as IRQ support was broken on both
RTL and zephyr side

* Interrupts are now synced to instruction lifetimes
* Interrupts are disabled on traps and mie is pushed to mpie
* Zephyr applications regenerated from rewritten Zephyr port
* Timer is 32-bit to avoid wrapping around too often
* MEPC was not read properly from CSR storage
 2019-11-19 11:06:50 +01:00
Olof Kindgren
603c168d9b Allow readback of GPIO signal 2019-11-19 10:46:30 +01:00
Olof Kindgren
ed02951b4d Add vcd_start parameter 2019-11-19 10:46:15 +01:00
Olof Kindgren
40e7855bac Add width and divider parameters to servant_timer 2019-11-19 10:46:03 +01:00
Olof Kindgren
1a961af5ac Only allocate used RF mem 2019-11-10 21:45:34 +01:00
Gwenhael Goavec-Merou
61c8a6b886 add arty_a7_35t support 2019-11-10 21:44:50 +01:00
Gwenhael Goavec-Merou
d90030b955 xilinx PLL: allows to specify PLL output frequency (16 or 32 MHz) 2019-11-10 21:44:50 +01:00
Gwenhael Goavec-Merou
1f6d215d19 README: argument to use blinky example instead of hello world is true for all boards 2019-11-10 15:36:15 +01:00
Gwenhael Goavec-Merou
cf187bc81e README: --firmware parameter only available for sim and verilator_tb targets 2019-11-07 09:05:33 +01:00
Fabien Marteau
529cf6192b path correction and little comment (#12) 
* path fixed

* Update README.md

Little comment to says that simulation should be stopped with Ctrl-C.

* Update README.md

adding dependencies

* Update README.md
 2019-11-05 10:04:59 +01:00
Olof Kindgren
9c83e39635 Initialize state of verilator UART decoder 2019-11-04 13:01:31 +01:00
Olof Kindgren
98bfcc3b62 Remove unused jalr signal 2019-10-30 09:07:58 +01:00