Olof Kindgren 3438e0f172 Optimize mcause CSR

2019-03-21 09:24:11 +01:00

..

ice40_pll.v

Fix clock generation

2018-12-06 22:12:03 +01:00

riscv_timer.v

Interrupts working. Adding philosophers example

2018-11-26 23:03:40 +01:00

ser_add.v

Use custom interconnect. Runs on hw

2018-11-21 13:15:33 +01:00

ser_lt.v

Fix bugs and missing resets to pass formal

2018-12-11 22:05:32 +01:00

ser_shift.v

Use bufreg for shifter

2019-03-20 08:35:43 +01:00

serv_alu.v

Optimize alu eq check

2019-03-20 08:35:43 +01:00

serv_bufreg.v

Use bufreg for shifter

2019-03-20 08:35:43 +01:00

serv_clock_gen.v

Syntax fixes to please Vivado

2018-12-07 23:20:47 +01:00

serv_csr.v

Optimize mcause CSR

2019-03-21 09:24:11 +01:00

serv_ctrl.v

Use ring buffer for counter LSBs

2019-01-15 08:00:32 +01:00

serv_decode.v

Use bufreg for shifter

2019-03-20 08:35:43 +01:00

serv_mem_if.v

Use bufreg for shifter

2019-03-20 08:35:43 +01:00

serv_params.vh

Rewrite CSR selection

2019-01-10 18:15:20 +01:00

serv_regfile.v

Remove dead code

2019-01-15 08:00:32 +01:00

serv_top.v

Use bufreg for shifter

2019-03-20 08:35:43 +01:00

shift_reg.v

Fix bugs and missing resets to pass formal

2018-12-11 22:05:32 +01:00

wb_gpio.v

Use custom interconnect. Runs on hw

2018-11-21 13:15:33 +01:00