Olof Kindgren 42ac1e5e4d Store CSR in RF RAM ...

Since FPGA uses fixed-size RAM, it's better in most cases to store
the CSR in unused memory positions in that RAM.

Since the decoding is made more complex, the old register file
implementation is kept around since that is more efficient when we
don't want CSR and potentially when the FPGA support hardware
shift registers.

2019-06-07 19:39:18 +02:00

..

ice40_pll.v

Fix clock generation

2018-12-06 22:12:03 +01:00

riscv_timer.v

Fix width mismatches to make code verilator clean

2019-03-25 20:57:13 +01:00

ser_add.v

Use custom interconnect. Runs on hw

2018-11-21 13:15:33 +01:00

ser_lt.v

Fix bugs and missing resets to pass formal

2018-12-11 22:05:32 +01:00

ser_shift.v

Fix width mismatches to make code verilator clean

2019-03-25 20:57:13 +01:00

serv_alu.v

Fix width mismatches to make code verilator clean

2019-03-25 20:57:13 +01:00

serv_bufreg.v

Fix width mismatches to make code verilator clean

2019-03-25 20:57:13 +01:00

serv_clock_gen.v

Fix width mismatches to make code verilator clean

2019-03-25 20:57:13 +01:00

serv_csr.v

Store CSR in RF RAM

2019-06-07 19:39:18 +02:00

serv_ctrl.v

Speed up instruction fetching

2019-04-12 08:15:08 +02:00

serv_decode.v

Use bufreg for shifter

2019-03-20 08:35:43 +01:00

serv_mem_if.v

Use bufreg for shifter

2019-03-20 08:35:43 +01:00

serv_mpram.v

Store CSR in RF RAM

2019-06-07 19:39:18 +02:00

serv_params.vh

Rewrite CSR selection

2019-01-10 18:15:20 +01:00

serv_regfile.v

Remove dead code

2019-01-15 08:00:32 +01:00

serv_top.v

Store CSR in RF RAM

2019-06-07 19:39:18 +02:00

shift_reg.v

Fix bugs and missing resets to pass formal

2018-12-11 22:05:32 +01:00

wb_gpio.v

Use custom interconnect. Runs on hw

2018-11-21 13:15:33 +01:00