Originally, the VAX allowed immediate operands (8F) to be used without
restrictions in address mode instructions, either standalone or indexed.
Starting with MicroVAX II, immediate indexed became reserved. This
remained true for all subsequent chip implementations. The SRM was
ECOed in March, 1985 to make immediate indexed unpredictable.
In MicroVAX II, immediate g-floating operands didn't work correctly. The
problem was found a couple of months after tape-out. While the index
flows could be fixed, and were fixed according to the microcode revision
history:
; 7-May-84 [RMS] Fixed FD problem in index flows (JLR)
the problem in indexed immediate could only be fixed by a significant
hardware change in an area that was already packed full. The VAX
Architecture Team, which had always been very sympathetic to the
VAX chip efforts, proposed a much simpler solution: make immediate
indexed unpredictable. It was useless, in any case.
I'm rather surprised that this wasn't flagged by the 780 diagnostics.
Maybe it was never tested. It was tested in HCORE (the original MicroVAX I
core diagnostic that is failing), but I removed it subsequently:
; 8-may-85 rms removed indexed immediate tests
Bottom line - the simulator is right for the chip VAXes (including, I think,
V11) and wrong for MicroVAX I and probably the 8600, 780, 750, and 730.
As originally specified, both MTPR and MFPR set N,Z based on the
transmitted/received longword data, cleared V, and left C untouched. The
simulator hardwired this (except for the standardized TBCHK register)
based on the CVAX microcode.
In the 8200, accessing the RXCD register sets V for character
sent/received. (The VAX vector MxPRs also return non-standard values
for the condition codes.) This is one of the reasons that, in 1986, the
VAX architecture spec was changed to make the condition codes
UNPREDICTABLE following MTPR or MFPR.
Accordingly, I've added a "hook" to support the 8200 and other
non-standard MxPRs: global variable mxpr_cc_vc.
At the start of MTPR or MFPR (only), this variable is set to
000<current C bit>. MTPR will set N and Z based on the transmitted
operand and clear V and C. MFPR will set N and Z based on the received
data and clear V and C. Then, at the end, mxpr_cc_vc, masked down to
V & C, is ORed into the condition codes.
Thus, if an IPR write or read does nothing special, MTPR and MFPR will
get the canonical results. N,Z set, V cleared, C preserved. However, an
IPR routine can now specify a non-standard value for V and/or C by
modifying mxpr_cc_vc.
This tweak required changes only in vax_cpu.c. None of the model-
specific IPR routines need to be changed, except for Matt's 8200 RXCD
code. Anyone attempting implementation of further models (or VAX
vectors) should be aware of this new capability.
3.10 is mostly an attempt to get aligned with the current head of the
GitHub 4.0 sources. While the core libraries and SCP have diverged too
far for real forward and backward compatibility, enough 4.0 workalikes
have been added to allow much closer convergence of the two streams.
3.10 will provide the basis for my future simulation work.
- Windows did not validate that the a segment size was correct.
- Add shared memory object name to the management structure
- Linux shared memory object names must start with a /
- Linux umask setting to assign permissions
- Add textual explanations for failure cases
3.10 is mostly an attempt to get aligned with the current head of the
GitHub 4.0 sources. While the core libraries and SCP have diverged too
far for real forward and backward compatibility, enough 4.0 workalikes
have been added to allow much closer convergence of the two streams.
3.10 will provide the basis for my future simulation work.
The SDS tape unit can't do write reverse (no magtape tape can, afaik).
So instead of testing for a particular write subop, the code just tests
that the write was done in BCD mode.
This is closer to how the hardware works.
Most history routines defined a local sim_eval of the proper length, but the
erroneous ones were fixed length machines that defined an integer variable
instead of an integer array of length 1. The VAX used the global sim_eval.
The changes follow the VAX practice.
The major change is the implementation of deferred IO - a more
accurate implementation of the 1620's "stop in its tracks" IO model.
When a device uses deferred IO, instruction execution is suspended
until the IO completes successfully. Operator interruptions, errors,
and so on do not return to instruction execution; this only occurs if
the IO completes successfully or the command SET CPU RELEASE is given
(equivalent of pressing the RELEASE button). Otherwise, the current IO
operation continues to execute.
Only the console typewriter and paper tape reader/punch currently
implement deferred IO; there are operational issues with those devices
that require more accurate modeling. The card reader/punch, line
printer, and disk still execute IO "instantaneously". It's not all
that hard to convert an instantaneous device to deferred operation,
but there's no point in doing so (and possibly introducing new bugs)
unless there's an actual operational issue. The 1620 doesn't have
overlapped IO, so programs can't tell the difference, by and large.
A number of other issues have been addressed as well, including the
bizarre "treat RM as 0 in the Q field" required by MI-015; the
treatment of non-existent indicators as always off; and various other
tweaks.
I've run CU01 (again), which at least gives typewriter and paper-tape
IO a basic workout; and it works. I leave more detailed testing to
people who know the machine better than I do.
The documentation has been updated to include Tom's detailed breakdown
of IO handling for all IO operations on the typewriter, paper-tape
reader/punch, card reader/punch, and line printer.
It turns out that the two reversed opcodes Maurice identified were not the
only problems in opcode 12 (shifts). All of the INS/EXT pairs at function
codes .57 and above were reversed. In addition, the mnemonics in the
opcode table in alpha_sys.c are wrong as well as reversed.
- Changed to commit PC on certain stops
- Added SET CPU RELEASE command
- Undefined indicators don't throw an error (Dave Wise)
- Added Model I mode to allow record marks in adds (Dave Wise)
- Allowed undocumented indicator 8 (Dave Wise)
- Added option for Model I diagnostic mode (Dave Wise)
