added INCRP macro - now does 32-bit increments of RP for speed
added ADDRP macro to return RP incremented by n (CGT)
changed globals to static (didn't help speed much - thought it might)
moved around some functions
changed shift instructions to create bitmask at runtime (faster)
manually inlined mathexception (but used inline keyword in later revs)
changed get16/put16 to get16t/put16t where address trap might occur
this eliminates ea<0 test for all other non-trappable get16/put16 calls
changed crs & crsl to macros to reference a union vs 2 distinct variables
changed crs and RP to be register variables (regs.h)
fixed tape drive problems
added "smart" LRU code to handle multiple register sets
expanded registers to handle 8 user, 2 system (10 total)
turned off various process-exchange changes that were causing failures
only zero first 64K of memory
added emulation of ZTRN, ZED, and RTS
started I-mode floating point
make sure R-mode MPL faults to appease DIAG tests
added IOTLB, mapio, and get/put16io macros so rev23 would boot
changed device drivers to go through IOTLB, not STLB
removed SVC Primos II emulation code
changed floating point register format to match memory
added T_TERM for system terminal output tracing
added specific user tracing:
- 2-digit number after trace (user number)
- 6-digit octal number = OWNERL (for devices)
added specific procedure tracing
major bug in PCL: indirect bit offsets not working,
causing SAC JIM:PDALURW to be SAC JIM:PAUW
need to restore interval timer when new process dispatched
process level was incorrect when new process dispatched
changes setting process abort flag in PCB when timer overflows
tracing for address translation, disk I/O, and PCL
field address, field length, and load/store character instructions
queue instructions
more work on setting C & L bits correctly
added live register access flag to effective address calculations
first attempt at complete 64V address calculation
first RSAV/RRST, STAC/STLC, LPSW, LDLR/STLR, EIO
more shift instruction work
