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30 Commits

Author SHA1 Message Date
Dennis Boone
43d2d863d7 Replace tabs with spaces
Mixed tabs/spaces gets hairy.  I've expanded the tabs on the basis
of 8-position tabstops.
2020-05-30 01:42:39 -04:00
Jim
9054d69446 em.c, etc: use gv.xxx instead of gvp->xxx for 13% speed increase, from
37.5 Prime MIPS on Linode VM to 42.5 MIPS.  gvp-> was faster on the
PowerPC architecture when gvp was kept in a dedicated register, but
that does not apply to Intel.

Old:

Timing CPU,  20.0 ticks per second...
  35.3 Prime MIPS for 16-bit ADD loop
  40.0 Prime MIPS for 16-bit MPY loop
  42.1 Prime MIPS for 16-bit DIV loop
  21.4 Prime MIPS for 32-bit ADD loop
  30.8 Prime MIPS for 32-bit MPY loop
  28.6 Prime MIPS for 32-bit DIV loop
  57.1 Prime MIPS for 16-bit X=0 loop
  44.4 Prime MIPS for 32-bit X=0 loop
  37.5 average Prime MIPS

New:

Timing CPU,  20.0 ticks per second...
  42.9 Prime MIPS for 16-bit ADD loop
  53.3 Prime MIPS for 16-bit MPY loop
  47.1 Prime MIPS for 16-bit DIV loop
  24.0 Prime MIPS for 32-bit ADD loop
  38.1 Prime MIPS for 32-bit MPY loop
  32.0 Prime MIPS for 32-bit DIV loop
  57.1 Prime MIPS for 16-bit X=0 loop
  44.4 Prime MIPS for 32-bit X=0 loop
  42.4 average Prime MIPS
2020-03-08 23:46:14 -04:00
Jim
a4cc429fad Linux cleanup to remove demo/dongle code, remove PowerPC stuff, fix slow PNC I/O, fix a nasty devmt bug 2020-02-24 23:55:03 -05:00
Jim
ff791c1b9c Remove bogus var from ea64v.h, add quit handler to flush trace buffers 2011-10-19 11:02:23 -04:00
Jim
2a89fb6ab8 First set of byte-swap changes; should compile equal to version 194 2011-10-17 10:53:58 -04:00
Jim
bcfdbec10f Changes for gcc on OSX 10.6, cross compile on Intel 2011-07-18 09:31:14 -04:00
Jim
dd587bade1 Fixed if/else indenting 2008-10-04 17:49:42 -04:00
Jim
73eaf5cfd5 jump directly to shift to eliminate a sub-switch (Primos rebuild gcov)
After profiling Primos rebuild, shift instructions are #8
2007-10-21 00:00:00 -04:00
Jim
dffe43212e used gcov info to reorder some stuff in ea64v (ea64v4.h) 2007-10-12 00:00:00 -04:00
Jim
afdf6057b1 FP exceptions, -DNOREG for -O0 and -DBG compiles, perf tweaks, gcov
reworked ring/register fix so that Primos nevers sees RP faulted
  but we don't have to do extra tests in the fetch loop
changed EAxxx routines to use RP segno when EA = register
added FP exception fault to ieeepr8 and all FP routines
added round flag to ieeepr8 (though not sure it's rounding correctly)
used gcov info to reorder some stuff in ea16s, ea32s, ea32r64r
changed warn() and fatal() to use get16t; prevpc might be a register
IMPORTANT NOTE: to compile with -O0, also use -DNOREG (gcc bug)
2007-10-12 00:00:00 -04:00
Jim
36254e2fba RP ring bits weren't being preserved when executing code in registers.
This caused a HLT instruction in the register to halt the machine from ring 3
2007-10-09 00:00:00 -04:00
Jim
c845fdce12 changed main loop to test inhcount only when intvec is set;
this also required changes to emdev.h (can't look at inhcount)
2007-10-04 00:00:00 -04:00
Jim
d99d16932d More performance tweeaks: get/put(16/32)r, eaxxx()
changed get/put(16,32)r to check for ring change and use regular
  get/put call if possible, so brp supercache can be used
FUTURE: could add separate brp cache entry for R0 accesses
changed ea32r64r live register test so normal path is first
changed ea64v live register test so normal path is first
change ea32i to use INCRP macro instead of RPL++
2007-09-15 00:00:00 -04:00
Jim
7a713e8ea9 speedup LDC/STC, STTM CPU time fix, IMA/IRS perf, apea() perf, -DNOMEM
added 2 new rbp entries for FAR0/1; used in ldc/stc
changed IMA and IRS back to use get/put16t to make use of
  supercache instead of always doing 1 mapva
changed apea() to use brp[RPBR] for AP fetch, UNBR for indirect
added -DNOMEM to remove -mem command option and testing
fixed bug in STTM causing sporadic CPU times (negative deltas)
2007-09-14 00:00:00 -04:00
Jim
c4f7df2944 Fine tune eap supercache, other performance optimizations +
Change tracing to show when supercache is used
Symbolic names for supercache entries
Added supercache entries for sector 0 and PB (different from RP)
Add invalidate_brp to invalidate supercache
Separate get16trap (WILL trap) from get16t (MIGHT trap)
Use supercache in get32 and various get/put routines
2007-09-10 00:00:00 -04:00
Jim
84ae6fc905 eap register and gvp->brp page cache: 5 entries for PB, SB, LB, XB, "other"
removed "char unmodified" from STLB; uses access[2] instead, to
  avoid a multiply instruction in mapva (can use shift now)
use ea instead of pa when checking for page crossing in get32,
  in preparation for read VA caching, like iget16 uses
2007-09-09 00:00:00 -04:00
Jim
6afd8f2c52 added inline to shift procedures (reduced the executable size, + faster) +
changed gvp->prevppa from Prime memory offset to mem[] pointer
added inline to tch, tcr, adlr
added -DNOIDLE to make BDX use CPU cycles instead of sleeping
changed ea64v.h so ixy avoids branching (hot spot in Shark)
2007-09-07 00:00:00 -04:00
Jim
24179fd2ac added dispatch table for SRV memory references instructions vs switch +
inlined and simplified iget16 instruction fetch
moved pio test to R-mode path
moved and simplified effective address calculation switch stmt
removed mode switch stmt for EA calcs, changed to cascaded if
moved iget16 static vars to gvp, for inlining
changed mapva and iget16 so that the normal path is predicted
2007-09-05 00:00:00 -04:00
Jim
3e4c98c296 Added gvp->livereglim to speed up "live register" addressing mode tests 2007-09-02 00:00:00 -04:00
Jim
fdb4d4ae4c New ea64v, missing memory check, #ifdef FAST 2007-09-02 00:00:00 -04:00
Jim
0ea78958b0 Backout ea64v changes, PCL fixes, disabled curtrack/maxtrack check in devdisk 2007-09-01 00:00:00 -04:00
Jim
62b8229961 gvp dedicated global variable register, iget16 page cache 2007-08-31 00:00:00 -04:00
Jim
7601dcb718 INCRP, ADDRP macros, code optimization
added INCRP macro - now does 32-bit increments of RP for speed
added ADDRP macro to return RP incremented by n (CGT)
changed globals to static (didn't help speed much - thought it might)
moved around some functions
changed shift instructions to create bitmask at runtime (faster)
manually inlined mathexception (but used inline keyword in later revs)
2007-08-25 00:00:00 -04:00
Jim
8c0020d0dd get/put16t, crs/crsl macro, PowerPC register variables, tape bugs
changed get16/put16 to get16t/put16t where address trap might occur
this eliminates ea<0 test for all other non-trappable get16/put16 calls
changed crs & crsl to macros to reference a union vs 2 distinct variables
changed crs and RP to be register variables (regs.h)
fixed tape drive problems
2007-08-23 00:00:00 -04:00
Jim
319b868345 added ea32i.h include file, ea64v, devamlc, PNC
ea64v never needs to return a bit offset
added devamlc feature to set room available in user's input buffer
misc PNC changes (not working yet)
2007-04-19 00:00:00 -04:00
Jim
ec2ba390d0 MPY, DIV, devasr, devamlc changes +
for R-mode MPY, do the math THEN generate the exception
DIV exception handling was wrong, code was wrong too
a few devasr changes
changed devamlc to always turn off parity instead of flipping it
2007-02-25 00:00:00 -05:00
Jim
4b76c2ea1d changed fprintf(stderr... to TRACE macro
writes tracing to a buffered log file instead of stderr
added clear of first 32K of physical memory to master clear
changed all exit() calls to fatal() calls
more changes to the devmt tape driver
2007-02-18 00:00:00 -05:00
Jim
4703c0b8fd extensive changes to devmt tape controller emulation
changed to use iget16 instead of get16 to fetch instructions
added test in notify for semaphore overflow - call fatal()
2007-02-07 00:00:00 -05:00
Jim
6146f076fc Enhanced load map routines to print nearest symbol
Boots rev 20 (driveb) using --ss 14314, gets an uncorrected
disk read error, then hangs.
It also exhibits various failures in the file "fail".
2005-08-25 00:00:00 -04:00
Jim
8648e7426b moved ea64v to an include file ea64v.h
implemented stack extensions
more PCL/fault work
more PX work
more FP work
2005-08-19 00:00:00 -04:00