github.com/rdolbeau.SBusFPGA
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Oups forgot the DMA engine (this version with wishbone Converter)

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Romain Dolbeau 2021-07-18 02:47:15 -04:00
parent 0bd6b69dd9
commit b86cf18e19
1 changed files with 2 additions and 2 deletions
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sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
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@ -197,8 +197,8 @@ class SBusFPGA(SoCCore):
self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys)
self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
self.bus.add_master(name="mem_read_master", master=self.exchange_with_mem.wishbone_r_master)
self.bus.add_master(name="mem_write_master", master=self.exchange_with_mem.wishbone_w_master)
self.bus.add_master(name="mem_read_master", master=self.exchange_with_mem.wishbone_r_slave)
self.bus.add_master(name="mem_write_master", master=self.exchange_with_mem.wishbone_w_slave)
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",