Romain Dolbeau b86cf18e19 Oups forgot the DMA engine (this version with wishbone Converter)

2021-07-18 02:47:15 -04:00

..

forth_to_migen_rom.sh

prom

2021-07-14 05:14:19 -04:00

netbsd_csr.h

access the SDRAM using a custom DMA; unreliable yet

2021-07-17 11:03:44 -04:00

prom_csr.fth

access the SDRAM using a custom DMA; unreliable yet

2021-07-17 11:03:44 -04:00

prom_migen.bth

prom

2021-07-14 05:14:19 -04:00

prom_migen.fth

access the SDRAM using a custom DMA; unreliable yet

2021-07-17 11:03:44 -04:00

sbus_to_fpga_blk_dma.py

Oups forgot the DMA engine (this version with wishbone Converter)

2021-07-18 02:47:06 -04:00

sbus_to_fpga_export.py

fix export for driver

2021-07-14 06:36:35 -04:00

sbus_to_fpga_fsm.py

access the SDRAM using a custom DMA; unreliable yet

2021-07-17 11:03:44 -04:00

sbus_to_fpga_soc.py

Oups forgot the DMA engine (this version with wishbone Converter)

2021-07-18 02:47:15 -04:00

sdram_csr.fth

prom

2021-07-14 05:14:19 -04:00

sdram_init.fth

prom

2021-07-14 05:14:19 -04:00

ztex213_sbus.py

read PROM from Wishbone (simplify things, save resources as it was mapped there already anyway), add sd_card (unused, un-promed yet)

2021-07-14 08:30:27 -04:00