6 Commits

Author	SHA1	Message	Date
wfjm	22bb8e011c	reorganize dcm/mmcm/ppl sim models ... - sfs_gsim_core: new common simulation core - {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core - s7_cmt_sfs_tb: removed, use now sfs_gsim_core - rtl/bplib/*/tb/tb_*: use now sfs_gsim_core - tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core	2018-11-09 17:48:56 +01:00
wfjm	dfa2a91a18	get disclaimers in line with GPL V3 License.txt	2018-01-02 21:57:40 +01:00
Walter F.J. Mueller	238b6e4276	rename .cvsignore -> .gitignore	2016-12-17 16:28:37 +01:00
Walter F.J. Mueller	5983b0bb2a	- upgraded CRAM controller, now with 'page mode' support ... - new test bench driver tbrun, give automatized test bench execution	2016-10-15 07:42:21 +00:00
Walter F.J. Mueller	2b5cfb7d96	- Code base cleaned-up for vivado, fsm now inferred ... - xsim support complete (but many issues to be resolved yet) - Added configurable w11a cache - Removed some never documented and now strategically obsolete designs	2016-06-26 16:02:42 +00:00
Walter F.J. Mueller	e1479d4e5d	- Add Arty support (BRAM only) ... - Add sysmon/xadc support (for nexys4,basys3,arty designs) - Add Vivado simulator support (DPI not yet working)	2016-03-19 15:45:59 +00:00