4 Commits

Author	SHA1	Message	Date
Walter F.J. Mueller	29d2dc5bef	- interim release w11a_V0.561 (untagged) ... - Added simple simulation model of Cypress FX2 and test benches for functional verifcation of FX2 controller - Bugfixes in FX2 firmware and controller, works now also on Nexys3 & Atlys - Added test systems for rlink over USB verification for Nexys3 & Atlys	2013-01-06 16:19:26 +00:00
Walter F.J. Mueller	cbd8ce3468	- interim release w11a_V0.56 (untagged) ... - re-organized handling of board and derived clocks in test benches - added message filter definitions for some designs (.mfset files) - added Cypress EZ-USB FX2 controller (USB interface) - added firmware for EZ-USB FX2 supporting jtag access and data transfer - FPGA configure over USB now supported directly in make build flow - added test systems for USB testing and rlink over USB verification - no functional change of w11a CPU core or any pre-existing test systems - Note: Carefully read the disclaimer about usage of USB VID/PID numbers in the file README_USB-VID-PID.txt. You'll be responsible for any misuse of the defaults provided with the project sources !!	2013-01-02 21:06:53 +00:00
Walter F.J. Mueller	0f28defb8a	- final touch-up for V0.53 minor release	2011-04-17 12:32:28 +00:00
Walter F.J. Mueller	a20f49fcd5	- add sources for C++/Tcl based backend, add directories ... - tools/src/... - tools/tcl/... - tools/dox - tools/make - add rlink test system - rtl/sys_gen/tst_rlink/nexys2/...	2011-04-02 11:08:56 +00:00