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Commit Graph

6 Commits

Author SHA1 Message Date
Walter F.J. Mueller
238b6e4276 rename .cvsignore -> .gitignore 2016-12-17 16:28:37 +01:00
Walter F.J. Mueller
5983b0bb2a - upgraded CRAM controller, now with 'page mode' support
- new test bench driver tbrun, give automatized test bench execution
2016-10-15 07:42:21 +00:00
Walter F.J. Mueller
677773d123 - Add CPU debug and monitoring units (dmhbpt,dmscnt,dmcmon) 2015-12-30 20:21:18 +00:00
Walter F.J. Mueller
e91847f8db - added support for Vivado
- added support for Nexys4 and Basys3 boards
- added RL11 disk support
- lots of documentation updated
2015-03-09 19:26:25 +00:00
Walter F.J. Mueller
3f455d5236 - interim release w11a_V0.532 (untagged)
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
2011-11-20 12:31:43 +00:00
Walter F.J. Mueller
3335c61549 initial source upload (no docs yet) 2010-07-09 18:14:38 +00:00