9 Commits

Author	SHA1	Message	Date
wfjm	0ebc1c7403	SPDX: *.xdc	2019-07-26 18:03:23 +02:00
wfjm	d3cce101a7	SPDX: rtl/*/*.vhd	2019-07-12 19:01:49 +02:00
wfjm	3c92b79224	SPDX: Makefile(.ise)	2019-07-05 17:23:39 +02:00
wfjm	cb7b906089	Add memory tester for Arty and MIG ... - sys_tst_sram_arty: add system and tb - sramif_mig_arty: add SRAM to DDR via MIG adapter for arty - cdc_pulse: add clock domain crossing for a slowly changing value - cdc_vector_s0: add ENA port (now used in cdc_pulse) - tst_mig/util.tcl: test_rwait: add optional lena argument - viv_tools_build.tcl: downgrade SSN critical warnings to warnings	2019-01-03 09:15:07 +01:00
wfjm	14362b2a56	Add basic DDR memory support ... - arty board support - viv_tools_build: export log and rpt generated in OOC synthesis runs - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model	2018-12-31 10:00:14 +01:00
wfjm	e1abc27983	comment&code cosmetics; minor changes	2018-11-11 09:50:46 +01:00
wfjm	dfa2a91a18	get disclaimers in line with GPL V3 License.txt	2018-01-02 21:57:40 +01:00
Walter F.J. Mueller	92e149437d	Fix license disclaimer	2016-12-26 21:27:33 +01:00
Walter F.J. Mueller	2b5cfb7d96	- Code base cleaned-up for vivado, fsm now inferred ... - xsim support complete (but many issues to be resolved yet) - Added configurable w11a cache - Removed some never documented and now strategically obsolete designs	2016-06-26 16:02:42 +00:00