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wfjm.w11/rtl/bplib/arty
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wfjm 563e230a6a get Nexys A7 working and integrated 
- rtl/bplib
  - arty/migui_arty_gsim.vhd: cosmetics
  - nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
  - nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
  - tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
  - tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
  - w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
  - */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
  - sys_w11a_arty_setup.tcl: add missing memsize definition
  - sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
2019-08-10 19:03:47 +02:00
..
tb
SPDX: rtl/*/*.vhd
2019-07-12 19:01:49 +02:00
arty_pclk.xdc
SPDX: *.xdc
2019-07-26 18:03:23 +02:00
arty_pins.xdc
SPDX: *.xdc
2019-07-26 18:03:23 +02:00
arty_setup.tcl
SPDX: rest
2019-07-26 18:06:36 +02:00
artylib.vhd
SPDX: rtl/*/*.vhd
2019-07-12 19:01:49 +02:00
mig_a.prj
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
mig_arty.tcl
SPDX: rest
2019-07-26 18:06:36 +02:00
miglib_arty.vbom
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
miglib_arty.vhd
SPDX: rtl/*/*.vhd
2019-07-12 19:01:49 +02:00
migui_arty_gsim.vbom
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
migui_arty_gsim.vhd
get Nexys A7 working and integrated
2019-08-10 19:03:47 +02:00
sramif_mig_arty.vbom
Add memory tester for Arty and MIG
2019-01-03 09:15:07 +01:00
sramif_mig_arty.vhd
SPDX: rtl/*/*.vhd
2019-07-12 19:01:49 +02:00