mirror of
https://github.com/wfjm/w11.git
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563e230a6a
- rtl/bplib
- arty/migui_arty_gsim.vhd: cosmetics
- nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
- nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
- tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
- tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
- w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
- */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
- sys_w11a_arty_setup.tcl: add missing memsize definition
- sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
This directory sub-tree contains serial port loop back tester systems and is organized in
| Directory | Content |
|---|---|
| nexys2 | design for Digilent Nexys2 |
| nexys3 | design for Digilent Nexys3 |
| nexys4 | design for Digilent Nexys4 (old CRAM version) |
| nexys4d | design for Digilent Nexys4 DDR !! only sim-tested !! |
| s3board | design for Digilent S3BOARD |