mirror of
https://github.com/wfjm/w11.git
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674762d6d8
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs - sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs - tbcore_rlink: wait 40 cycles after CONF_DONE - serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
This directory tree contains all HDL sources and is organized in
| Directory | Content |
|---|---|
| bplib | support modules for boards or parts |
| ibus | w11 ibus devices |
| make_ise | make includes for ISE build flows |
| make_viv | make includes for Vivado build flows |
| sys_gen | HDL sources for top level designs |
| vlib | wide range of support modules |
| w11a | HDL sources for w11a core |