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674762d6d8
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs - sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs - tbcore_rlink: wait 40 cycles after CONF_DONE - serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
This directory sub-tree contains HDL sources for top level designs and is organized in
| Directory | Content |
|---|---|
| tst_rlink | rlink tester (over serial links) |
| tst_rlink_cuff | rlink tester (over Cypress FX2 USB) |
| tst_serloop | serial port loop back tester |
| tst_snhumanio | Digilent board human IO tester |
| tst_sram | memory tester (SRAM or CRAM) |
| w11a | w11a systems |