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674762d6d8
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs - sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs - tbcore_rlink: wait 40 cycles after CONF_DONE - serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
This directory sub-tree contains support modules for boards or parts and is organized in
| Directory | Content |
|---|---|
| arty | support for Digilent Arty board |
| atlys | support for Digilent Atlys board |
| basys3 | support for Digilent Basys3 board |
| bpgen | interfaces for IO devices common on Digilent boards |
| cmoda7 | support for Digilent Cmod A7 board |
| fx2lib | interface for Cypress FX2 USB |
| fx2rlink | modules for rlink over Cypress FX2 |
| issi | simulation models for ISSI components |
| micron | simulation models for Micron components |
| nexys2 | support for Digilent Nexys2 board |
| nexys3 | support for Digilent Nexys3 board |
| nexys4 | support for Digilent Nexys4 board (cram version) |
| nxcramlib | interface for ISSI CRAM |
| s3board | support for Digilent S3BOARD board |
| sysmon | interface for Xilinx Series-7 sysmon |