wfjm 674762d6d8 consolidate clock generation in 7-Series designs ...

- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter

2018-12-21 09:06:16 +01:00

..

nexys2

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

nexys3

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

nexys4

consolidate clock generation in 7-Series designs

2018-12-21 09:06:16 +01:00

nexys4d

consolidate clock generation in 7-Series designs

2018-12-21 09:06:16 +01:00

s3board

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

tb

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

.gitignore

rename .cvsignore -> .gitignore

2016-12-17 16:28:37 +01:00

Makefile

- upgraded CRAM controller, now with 'page mode' support

2016-10-15 07:42:21 +00:00

Makefile.ise

- Code base cleaned-up for vivado, fsm now inferred

2016-06-26 16:02:42 +00:00

tbrun.yml

- upgraded CRAM controller, now with 'page mode' support

2016-10-15 07:42:21 +00:00

tst_serloop_hiomap.vbom

- interim release w11a_V0.562 (untagged)

2013-04-13 17:13:15 +00:00

tst_serloop_hiomap.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

tst_serloop.vbom

- interim release w11a_V0.562 (untagged)

2013-04-13 17:13:15 +00:00

tst_serloop.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

tst_serlooplib.vbom

- interim release w11a_V0.562 (untagged)

2013-04-13 17:13:15 +00:00

tst_serlooplib.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00