wfjm
674762d6d8
consolidate clock generation in 7-Series designs
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
2018-12-21 09:06:16 +01:00
..
2018-01-02 21:57:40 +01:00
2018-12-21 09:06:16 +01:00
2015-03-09 19:26:25 +00:00
2018-01-02 21:57:40 +01:00
2018-11-11 09:50:46 +01:00
2016-06-26 16:02:42 +00:00
2015-03-09 19:26:25 +00:00
2018-01-02 21:57:40 +01:00
2016-06-26 16:02:42 +00:00
2018-01-02 21:57:40 +01:00
2013-01-02 21:06:53 +00:00
2018-01-02 21:57:40 +01:00
2014-12-20 16:39:52 +00:00
2018-01-02 21:57:40 +01:00
2013-01-02 21:06:53 +00:00
2018-01-02 21:57:40 +01:00
2015-05-14 17:00:36 +00:00
2018-01-02 21:57:40 +01:00
2016-06-26 16:02:42 +00:00
2018-01-02 21:57:40 +01:00
2013-04-13 17:13:15 +00:00
2018-01-02 21:57:40 +01:00