Emil J. Tywoniak
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6bff991e00
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opt_expr: replace invert_map with signorm traversal
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2026-05-06 12:39:35 +02:00 |
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Emil J. Tywoniak
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23de03cea9
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signorm: add timers
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2026-05-06 12:14:48 +02:00 |
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Emil J. Tywoniak
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54ef1275bd
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rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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a52b8d2f91
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check: fix memory bug in $connect
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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6d37b670c9
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memory_bram: create blackboxes
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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b4b774f06f
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Revert "intel: register bram celltypes"
This reverts commit 16785a7f75.
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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00437b36eb
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Revert "tests: use memory -bram-register in tests/bram"
This reverts commit 24488a7011.
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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6bb72212d6
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Revert "memory: add -bram-register"
This reverts commit 2bc6ea7f37.
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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a2e6647339
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Revert "memory_bram: add -register"
This reverts commit b4b5093a14.
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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12e179bc20
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intel_alm: loosen tests
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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ec7375d2cb
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gowin: loosen tests
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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b995059cef
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flatten: disable signorm
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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df791a5ac4
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ecp5: loosen tests
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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c5ed5163b3
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nexus: loosen tests
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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7c083ff204
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xilinx_dsp: signorm compatibility
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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5d069fcb3a
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pmgen: hold sigmap pointer instead of owning it
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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e218c25b30
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gowin: rebless LUT counts
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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4e4700b456
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equiv_miter: don't copy $input_port
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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a3beac73f6
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rtlil_bufnorm: more xlog
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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25d127f0dc
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design: properly switch signorm mode when restoring saved designs
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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a39ab42b99
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equiv_make: don't copy $input_port
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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441a1f47fb
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rtlil: fix cloneInto in signorm
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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69ff2fb484
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rtlil: sigNormalize Module when added to Design in signorm mode
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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81617afa95
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rtlil_bufnorm: more xlog
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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a000a7830c
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intel: register bram celltypes
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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16877b61da
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rtlil_bufnorm: ignore timing info harder
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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1052e89772
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gowin: replace positional arguments in cells_sim.v with named
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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b4bb200dec
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Revert "techmap: call hierarchy on map files to determine port directions"
This reverts commit eabbf6d225.
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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0d62ac186c
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hierarchy: tolerance for apparent recursive instances in techmap files
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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38255da162
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techmap: call hierarchy on map files to determine port directions
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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e78a1a7b3d
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tests: use memory -bram-register in tests/bram
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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33e5d9340f
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memory: add -bram-register
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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23523603dc
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memory_bram: add -register
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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e3c428b6a9
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ffmerge: initvals signorm compatibility fixup
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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8e0a0db296
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timinginfo: special-case $specify2 in signorm invariant
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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d1c463d685
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opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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e4d532b886
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connect: remove input ports on conflict
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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708bc57e79
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opt_dff: sigma harder, FfDataSigMapped
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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274823041b
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ff: add FfDataSigMapped
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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b58952cf2a
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opt_dff: temporarily disable signorm due to muxtree traversal
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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451d8471b7
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tests: fix rtlil roundtrip test
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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a65d8fbcb9
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design: fix signorm commit connectivity to design
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2026-05-05 21:35:14 +02:00 |
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Emil J. Tywoniak
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992d20071b
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cxxrtl: ignore $input_port
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2026-05-05 21:35:13 +02:00 |
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Emil J. Tywoniak
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80baffb60e
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flatten: redo signormalization to work around fanout issue
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2026-05-05 21:35:13 +02:00 |
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Emil J. Tywoniak
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b8f2dfbd5c
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abstract: fix test signorm
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2026-05-05 21:35:13 +02:00 |
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Emil J. Tywoniak
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e75523bf61
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signorm: disable passes that use rewrite_sigspecs
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2026-05-05 21:35:13 +02:00 |
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Emil J. Tywoniak
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66af891caa
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aiger: ignore $input_port
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2026-05-05 21:35:13 +02:00 |
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Emil J. Tywoniak
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99f88aa7e8
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check: stitch info about $connect ports together for driver analysis
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2026-05-05 21:35:13 +02:00 |
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Emil J. Tywoniak
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e8144f16ac
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signorm: remove $input cells when leaving
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2026-05-05 21:35:13 +02:00 |
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Emil J. Tywoniak
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d001b407c4
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abstract: skip $input_port cells
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2026-05-05 21:35:13 +02:00 |
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