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Mono Color

• 0f5e7c244d add additional dff and lutram tests Miodrag Milanovic 2023-04-04 11:18:24 +02:00
• 54d313efc3 add test for CCU2D Miodrag Milanovic 2023-04-04 10:56:28 +02:00
• 9e9fae1966 Add more DFF types Miodrag Milanovic 2023-04-04 10:56:17 +02:00
• d5a405d3b4 Added proper simulation model for CCU2D Miodrag Milanovic 2023-04-03 12:58:29 +02:00
• 6e4c1675e7 Generate TRELLIS_DPR16X4 for lutram Miodrag Milanovic 2023-03-31 15:46:35 +02:00
• 6e12da3956 machxo2: Initial support for carry chains (CCU2D) Miodrag Milanovic 2023-03-31 13:36:36 +02:00
• bd06338172 py_wrap_generator: Fix handling of method name collisions Martin Povišer 2023-04-05 13:33:18 +02:00
• f94f544b50 Fix the python generator for a bunch of const cases Martin Povišer 2023-04-05 12:36:56 +02:00
• 53c0a6b780 Bump version github-actions[bot] 2023-03-24 00:16:02 +00:00
• f35bdaa527 Update Xilinx cell definitions, fixes #3699 Miodrag Milanovic 2023-03-21 08:53:22 +01:00
• 23826e5152 Bump version github-actions[bot] 2023-03-21 00:15:46 +00:00
• dc0a799c06 Merge pull request #3708 from jix/void_func Jannis Harder 2023-03-20 16:10:19 +01:00
• fb1c2be76b verilog: Support void functions Jannis Harder 2023-03-20 12:50:14 +01:00
• 61da330a38 Update tests Miodrag Milanovic 2023-03-18 18:12:02 +01:00
• ff9f1fb86e Start unification effort for machxo2 and ecp5 Miodrag Milanovic 2023-03-18 18:11:50 +01:00
• 4d7e9e2e5d Add additional iopad_external_pin attributes Miodrag Milanovic 2023-03-17 17:23:26 +01:00
• db367bd69e Add iopad_external_pin to some basic io primitives Miodrag Milanovic 2023-03-17 16:45:03 +01:00
• 10589c57bf insert IO buffers for ECP5, off by default Miodrag Milanovic 2023-03-17 16:15:43 +01:00
• ceef00c35e Bump version github-actions[bot] 2023-03-16 00:17:57 +00:00
• 57fb1f51b2 Merge pull request #3704 from jix/enum_values Miodrag Milanović 2023-03-15 10:54:19 +01:00
• 390d1c583a verific: Fix enum_values support and signed attribute values Jannis Harder 2023-03-14 19:13:18 +01:00
• 101d19bb6a Bump version github-actions[bot] 2023-03-11 00:15:30 +00:00
• c50f641812 Merge pull request #3682 from daglem/struct-member-out-of-bounds Jannis Harder 2023-03-10 16:14:56 +01:00
• baa3659ea5 ice40: Fix path delay definitions Stefan Riesenberger 2022-11-05 10:05:08 +01:00
• 1af7d6121f Added test for dynamic indexing within struct members Dag Lem 2023-03-08 20:25:39 +01:00
• b58664d441 Bump version github-actions[bot] 2023-03-07 00:18:51 +00:00
• 7c5ae560a8 Merge pull request #3684 from YosysHQ/fix-GIT_REV N. Engelhardt 2023-03-06 16:12:36 +01:00
• 368f2984cd Next dev cycle Miodrag Milanovic 2023-03-06 08:50:14 +01:00
• 5f88c218b5 Release version 0.27 yosys-0.27 Miodrag Milanovic 2023-03-06 08:47:51 +01:00
• 0d3423ddea Index struct/union members within corresponding wire chunks Dag Lem 2023-02-28 18:45:55 +01:00
• 9747e55d95 Bump version github-actions[bot] 2023-03-02 00:18:47 +00:00
• 3f173c2180 Makefile: fix GIT_REV extraction if Yosys is built as submodule. Catherine 2023-02-23 01:38:14 +00:00
• 981c934b5b Merge pull request #3690 from whitequark/smtbmc-help-opt N. Engelhardt 2023-03-01 09:59:01 +01:00
• 25ebefc2a6 Merge pull request #3692 from nakengelhardt/stat_q_fix N. Engelhardt 2023-03-01 09:49:36 +01:00
• 1a3ff0d926 Merge pull request #3688 from pu-cc/gatemate-reginit N. Engelhardt 2023-03-01 09:49:14 +01:00
• 57897927ff stat: pass down quiet arg N. Engelhardt 2023-02-28 17:12:55 +01:00
• bb28e48136 Merge pull request #3663 from uis246/master Miodrag Milanović 2023-02-28 06:56:01 +01:00
• 4ff9063145 Merge pull request #3652 from martell/elvds Miodrag Milanović 2023-02-28 06:55:25 +01:00
• 71c59d9fab Bump version github-actions[bot] 2023-02-28 00:17:33 +00:00
• 4bb173e256 yosys-smtbmc: support -h/--help (and exit with code 0). Catherine 2023-02-27 20:24:47 +00:00
• 21e87f7986 Merge pull request #3646 from YosysHQ/lofty/fix-3591 Miodrag Milanović 2023-02-27 16:26:57 +01:00
• 842cdad575 Merge pull request #3674 from YosysHQ/fix_wide_case N. Engelhardt 2023-02-27 16:04:11 +01:00
• 2ab3747cc9 fabulous: Add support for mapping carry chains gatecat 2023-02-20 12:49:48 +01:00
• 28c4aac234 run verific tests in test target Miodrag Milanovic 2023-02-27 09:27:04 +01:00
• d8cefec169 Added ranged case check Miodrag Milanovic 2023-02-23 15:04:31 +01:00
• 53a4f0fb56 Add test example Miodrag Milanovic 2023-02-23 14:58:02 +01:00
• a30894e5fa Handle more wide case selector types Miodrag Milanovic 2023-02-17 09:45:41 +01:00
• 8216b23fb7 Bump version github-actions[bot] 2023-02-24 00:16:59 +00:00
• ef8ed21a2e Merge pull request #3685 from YosysHQ/update-abc Catherine 2023-02-23 07:57:27 +00:00
• 5d9bd0af92 Update abc. Catherine 2023-02-23 01:48:08 +00:00
• 0f2d226ae9 Bump version github-actions[bot] 2023-02-21 00:17:40 +00:00
• c8966722d2 Merge pull request #3403 from KrystalDelusion/mem-tests N. Engelhardt 2023-02-20 18:27:24 +01:00
• f80920bd9f Genericising bug1836.ys KrystalDelusion 2022-07-25 10:21:00 +12:00
• 445a801a85 bug3205.ys removed KrystalDelusion 2022-07-25 10:12:30 +12:00
• 51c2d476c2 Removing extra default_nettype lines KrystalDelusion 2022-07-25 10:10:21 +12:00
• 8f6a06951c Fix for sync_ram_sdp not being final module KrystalDelusion 2022-07-11 12:31:38 +12:00
• 7f033d3c1f More tests in memlib/generate.py KrystalDelusion 2022-07-07 11:10:33 +12:00
• af1b9c9e07 Tests for ram_style = "huge" KrystalDelusion 2022-07-07 10:27:54 +12:00
• de2f140c09 Testing TDP synth mapping KrystalDelusion 2022-07-05 11:18:43 +12:00
• 48f4e09202 Asymmetric port ram tests with Xilinx KrystalDelusion 2022-07-07 10:22:14 +12:00
• ac5fa9a838 Addings tests for #1836 and #3205 KrystalDelusion 2022-05-10 10:31:42 +12:00
• 79043cb849 Out of bounds checking for struct/union members Dag Lem 2023-02-19 23:25:08 +01:00
• f0116330bc Bump version github-actions[bot] 2023-02-18 00:17:33 +00:00
• f30b539cc2 Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dreg N. Engelhardt 2023-02-17 18:40:22 +01:00
• fc56978703 Check DREG attribute Oliver Keszöcze 2023-02-17 17:54:41 +01:00
• 1cfedc90ce Bump version github-actions[bot] 2023-02-17 00:18:18 +00:00
• 25e7cb3bbb fabulous: Add CLK to BRAM interface primitives gatecat 2023-02-16 11:57:19 +01:00
• a20804c6ed Bump version github-actions[bot] 2023-02-16 00:17:37 +00:00
• 2c7ba0e752 gatemate: Enable register initialization Patrick Urban 2023-02-15 17:29:01 +01:00
• 1c667fab2b Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes Jannis Harder 2023-02-15 13:45:00 +01:00
• 1cedad7a68 Merge pull request #3675 from daglem/struct-item-queries Jannis Harder 2023-02-15 13:33:34 +01:00
• 68480dfa19 Merge pull request #3671 from zachjs/master Jannis Harder 2023-02-15 13:04:43 +01:00
• b562b54c14 dfflegalize: allow setting mince and minsrst args from scratchpad N. Engelhardt 2023-02-15 12:53:46 +01:00
• f8219289b2 Corrected tests for data and array queries on struct/union item expressions Dag Lem 2023-02-15 12:36:29 +01:00
• c1e12877f0 Support for data and array queries on struct/union item expressions Dag Lem 2023-02-09 19:27:51 +01:00
• 53bda9de54 Merge pull request #3661 from daglem/struct-array-range-offset Jannis Harder 2023-02-15 11:21:56 +01:00
• 59de4a0e7f Bump version github-actions[bot] 2023-02-15 00:17:48 +00:00
• ec94703619 Merge pull request #2995 from georgerennie/cover_precond Jannis Harder 2023-02-14 17:46:31 +01:00
• 85f611fb23 Merge pull request #3126 from georgerennie/equiv_make_assertions Jannis Harder 2023-02-14 17:15:55 +01:00
• b636af9751 chformal: Note about using -coverenable with the Verific frontend Jannis Harder 2023-02-14 17:09:53 +01:00
• f37073050b gatemate: Update CC_PLL parameters Patrick Urban 2023-02-14 07:59:48 +01:00
• 6a7d5257cd gatemate: Add CC_USR_RSTN primitive Patrick Urban 2023-02-14 07:58:59 +01:00
• 4cb27b1a3a gatemate: Ensure compatibility of LVDS ports with VHDL Patrick Urban 2023-02-14 07:51:31 +01:00
• e0bc25f1af Bump version github-actions[bot] 2023-02-14 00:17:45 +00:00
• d2032ac6fd Merge pull request #3669 from jix/fix-xprop-tests-yosys-call Jannis Harder 2023-02-13 17:55:36 +01:00
• 550a5b7b6b Update license Miodrag Milanovic 2023-01-05 16:04:07 +01:00
• 713b7d3e26 added support for latched output reset Miodrag Milanovic 2022-12-19 11:40:50 +01:00
• 131b557727 Initial implementation of synthesizable assertions Miodrag Milanovic 2022-12-19 08:54:47 +01:00
• 55ad3fe6c7 xprop tests: Make iverilog invocation more portable Jannis Harder 2023-02-13 16:50:27 +01:00
• 2a68eee5f1 xprop: Test fixes and abort on test failure Jannis Harder 2023-02-13 14:03:08 +01:00
• 9f20beb7df xprop: Smaller subset of tests to run by default Jannis Harder 2023-02-13 14:02:02 +01:00
• 160eeab2bb verilog_backend: Do not run bwmuxmap even if in expr mode Jannis Harder 2023-02-13 14:00:38 +01:00
• 1698202ccc sim: For yw cosim, drive parent module's signals for input ports Jannis Harder 2023-02-13 12:26:06 +01:00
• 4c334b905f Bump version github-actions[bot] 2023-02-13 00:17:46 +00:00
• 615adc4253 Resolve package types in interfaces (#3658) Dag Lem 2023-02-13 00:25:39 +01:00
• 26a6c60478 Add test for typenames using constants shadowed later on Zachary Snow 2023-02-12 17:03:37 -05:00
• 5ea2c290a5 Bump version github-actions[bot] 2023-02-11 00:14:42 +00:00
• 6d021f04d4 tests: Fix path of yosys invocation in xprop tests Jannis Harder 2023-02-10 19:17:16 +01:00
• f3c4e93d24 Merge pull request #3667 from jix/xprop-test-make-fix Jannis Harder 2023-02-10 16:06:16 +01:00
• d31d5da69f tests: in xprop tests, use MAKE variable if set Jannis Harder 2023-02-10 15:01:04 +01:00