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Commit Graph

  • b20bb653ce Bump version github-actions[bot] 2021-08-31 00:51:55 +00:00
  • f0a52e3dd2 sv: support declaration in procedural for initialization Zachary Snow 2021-08-30 11:35:36 -06:00
  • 1dbf91a8ef Bump version github-actions[bot] 2021-08-30 00:49:03 +00:00
  • 6de500ec08 [ECP5] fix wrong link for syn_* attributes description (#2984) kittennbfive 2021-08-29 09:45:23 +00:00
  • 591fe72203 Bump version github-actions[bot] 2021-08-23 00:46:01 +00:00
  • dfc453b246 Add DLLDELD ECP5-PCIe 2021-08-22 18:08:04 +02:00
  • 9cbff3a4a9 opt_merge: Remove and reinsert init when connecting nets. Marcelina Kościelnicka 2021-08-22 17:01:58 +02:00
  • 62d41d4639 opt_clean: Make the init attribute follow the FF's Q. Marcelina Kościelnicka 2021-08-21 23:36:00 +02:00
  • 21e710eb55 Bump version github-actions[bot] 2021-08-21 00:48:23 +00:00
  • c2d358484f Gowin: deal with active-low tristate (#2971) Pepijn de Vos 2021-08-20 21:21:06 +02:00
  • c2866780d2 Merge pull request #2973 from YosysHQ/micko/optional_extensions Miodrag Milanović 2021-08-20 16:09:55 +02:00
  • b59c427348 Make Verific extensions optional Miodrag Milanovic 2021-08-20 10:19:04 +02:00
  • 75a4cdfc8a Bump version github-actions[bot] 2021-08-18 00:51:20 +00:00
  • 3806b07303 ice40: Fix typo in SB_CARRY specify for LP/UltraPlus Sylvain Munaut 2021-08-17 10:21:04 +02:00
  • e6dd4db0af Bump version github-actions[bot] 2021-08-17 00:49:33 +00:00
  • 10f8b75dca kernel/mem: Remove old parameter when upgrading $mem to $mem_v2. Marcelina Kościelnicka 2021-08-16 12:31:01 +02:00
  • 83c0f82dc8 Bump version github-actions[bot] 2021-08-15 00:50:04 +00:00
  • faacc7ad89 proc_prune: Make assign removal and promotion per-bit, remember promoted bits. Marcelina Kościelnicka 2021-08-14 14:23:12 +02:00
  • 539d4ee907 Bump version github-actions[bot] 2021-08-14 00:46:42 +00:00
  • ee2b5b7ed1 Generate an RTLIL representation of bind constructs Rupert Swarbrick 2020-04-20 16:06:53 +01:00
  • f791328506 Add opt_mem_widen pass. Marcelina Kościelnicka 2021-08-13 00:43:15 +02:00
  • 1f74ec3535 memory_share: Add -nosat and -nowiden options. Marcelina Kościelnicka 2021-05-29 17:45:05 +02:00
  • 9fdedf4d1c memory_dff: Recognize soft transparency logic. Marcelina Kościelnicka 2021-08-10 19:42:10 +02:00
  • 616ace2d92 Add new opt_mem_priority pass. Marcelina Kościelnicka 2021-08-12 03:31:56 +02:00
  • 30927df881 Merge pull request #2932 from YosysHQ/mwk/logger-check-expected Miodrag Milanović 2021-08-13 11:45:20 +02:00
  • 979053855c sv: improve support for wire and var with user-defined types Brett Witherspoon 2021-06-22 09:51:41 -05:00
  • c8023e37d8 Bump version github-actions[bot] 2021-08-13 00:50:48 +00:00
  • d0d9aca2c3 memory_share: Pass addresses through sigmap_xmux everywhere. Marcelina Kościelnicka 2021-08-12 23:06:51 +02:00
  • c58ac63c97 logger: Add -check-expected subcommand. Marcelina Kościelnicka 2021-08-12 17:36:03 +02:00
  • bfcd08a323 Bump version github-actions[bot] 2021-08-12 00:49:51 +00:00
  • b98376884e test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. Marcelina Kościelnicka 2021-08-11 14:14:45 +02:00
  • 72d86c327e memory_dff: Recognize read ports with reset / initial value. Marcelina Kościelnicka 2021-05-27 21:08:11 +02:00
  • 24027b5446 proc_memwr: Use the v2 memwr cell. Marcelina Kościelnicka 2021-05-27 20:55:09 +02:00
  • fd79217763 Add v2 memory cells. Marcelina Kościelnicka 2021-05-27 20:54:29 +02:00
  • b96eb888cc Bump version github-actions[bot] 2021-08-11 00:52:20 +00:00
  • e6f3d1c225 kernel/mem: Introduce transparency masks. Marcelina Kościelnicka 2021-07-31 23:21:37 +02:00
  • 681a1c07e5 Allow optional comma after last entry in enum Michael Singer 2021-08-05 21:02:35 +02:00
  • f368e2c7e6 Bump version github-actions[bot] 2021-08-10 00:52:49 +00:00
  • d25b9088c8 Refactor common parts of SAT-using optimizations into a helper. Marcelina Kościelnicka 2021-08-04 00:02:16 +02:00
  • d8fcf1ab25 Bump version github-actions[bot] 2021-08-08 00:50:48 +00:00
  • 98003430d6 opt_merge: Use FfInitVals. Marcelina Kościelnicka 2021-08-08 00:33:31 +02:00
  • a24906a7d2 Bump version github-actions[bot] 2021-08-07 00:45:55 +00:00
  • 52cbf1bea5 verilog: Support tri/triand/trior wire types. Marcelina Kościelnicka 2021-08-06 20:49:41 +02:00
  • 2e421feb0e Bump version github-actions[bot] 2021-08-05 00:51:08 +00:00
  • 63f9e0544f memory_share: Don't skip ports with EN wired to input for SAT sharing. Marcelina Kościelnicka 2021-08-04 03:33:41 +02:00
  • d8b0c3277f Bump version github-actions[bot] 2021-08-04 00:49:53 +00:00
  • 8733e1923a memory_bram: Move init data swizzling before other swizzling. Marcelina Kościelnicka 2021-08-03 14:28:10 +02:00
  • ca8ad62696 Bump version github-actions[bot] 2021-08-03 00:55:22 +00:00
  • be04d8834e Require latest verific Miodrag Milanovic 2021-08-02 10:29:16 +02:00
  • 10bcc4e192 Bump version github-actions[bot] 2021-08-02 00:50:24 +00:00
  • ec2a468bd3 backend/verilog: Add alternate mode for transparent read port output. Marcelina Kościelnicka 2021-05-25 23:42:58 +02:00
  • 4451f7f5e9 memory_bram: Some refactoring Marcelina Kościelnicka 2021-08-01 01:29:49 +02:00
  • 12db9b4273 Bump version github-actions[bot] 2021-07-31 00:50:30 +00:00
  • c4a295cb8d Update version.yml Miodrag Milanović 2021-07-30 19:50:02 +02:00
  • cfddef5d7d Fixes xc7 BRAM36s Maciej Dudek 2021-07-29 21:10:02 +02:00
  • c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards Zachary Snow 2021-07-28 17:34:24 -04:00
  • 4fec3a85cd genrtlil: add width detection for AST_PREFIX nodes Zachary Snow 2021-07-29 12:35:22 -04:00
  • 87ef1dd805 Bump version github-actions[bot] 2021-07-30 00:52:33 +00:00
  • 54e75129e5 opt_lut: Allow more than one -dlogic per cell type. Marcelina Kościelnicka 2021-07-29 16:55:15 +02:00
  • 3156226233 verilog: save and restore overwritten macro arguments Zachary Snow 2021-07-15 10:36:50 -04:00
  • a055145b95 Bump version github-actions[bot] 2021-07-29 00:49:14 +00:00
  • 8bdc019730 verilog: Emit $meminit_v2 cell. Marcelina Kościelnicka 2021-05-21 02:27:06 +02:00
  • e9effd58d2 backends/verilog: Support meminit with mask. Marcelina Kościelnicka 2021-07-12 20:43:09 +02:00
  • 19720b970d memory: Introduce $meminit_v2 cell, with EN input. Marcelina Kościelnicka 2021-05-21 02:26:52 +02:00
  • 37d76deef1 Bump version github-actions[bot] 2021-07-28 00:52:46 +00:00
  • a0e912ba99 proc: Run opt_expr at the end Marcelina Kościelnicka 2021-07-27 15:43:36 +02:00
  • 436d42c00c opt_expr: Propagate constants to port connections. Marcelina Kościelnicka 2021-07-27 15:24:48 +02:00
  • 9600f20be8 Bump version github-actions[bot] 2021-07-27 00:52:14 +00:00
  • 45968ad740 Add version bump workflow Miodrag Milanovic 2021-07-26 11:25:32 +02:00
  • 987fca5297 Update to latest verific Miodrag Milanovic 2021-07-21 09:46:53 +02:00
  • 7a25246a7e Use new read_id_num helper function elsewhere in hierarchy.cc Rupert Swarbrick 2021-07-19 09:23:41 +01:00
  • 8fd6b45a3c Extract connection checking logic from expand_module in hierarchy.cc Rupert Swarbrick 2020-05-27 15:54:42 +01:00
  • a04844bdf8 Merge pull request #2885 from whitequark/cxxrtl-fix-2883 whitequark 2021-07-20 13:12:11 +00:00
  • 72beee2ccc Merge pull request #2884 from whitequark/cxxrtl-fix-2882 whitequark 2021-07-20 13:12:03 +00:00
  • 1a6ddf7892 cxxrtl: treat wires with multiple defs as not inlinable. whitequark 2021-07-20 10:30:39 +00:00
  • 225af830c1 cxxrtl: treat assignable internal wires used only for debug as locals. whitequark 2021-07-20 10:10:42 +00:00
  • c2afcbe78d Merge pull request #2881 from whitequark/cxxrtl-sideways-colon whitequark 2021-07-20 09:30:08 +00:00
  • fc84f23001 cxxrtl: escape colon in variable names in VCD writer. whitequark 2021-07-19 16:20:49 +00:00
  • 9af88951bc Merge pull request #2880 from whitequark/cxxrtl-fix-2877 whitequark 2021-07-18 07:35:23 +00:00
  • 948fc10d7b cxxrtl: add debug_item::{get,set}. whitequark 2021-07-18 06:07:27 +00:00
  • 101d72ccb3 Merge pull request #2879 from whitequark/cxxrtl-fix-2739-again whitequark 2021-07-17 17:22:15 +00:00
  • 4aa65f406f cxxrtl: treat internal wires used only for debug as constants. whitequark 2021-07-17 14:23:57 +00:00
  • 414154dd27 Add support for parsing the SystemVerilog 'bind' construct Rupert Swarbrick 2020-05-21 17:36:29 +01:00
  • 2db4137514 Merge pull request #2874 from whitequark/cxxrtl-fix-2589 whitequark 2021-07-16 11:12:19 +00:00
  • efc43270fa Merge pull request #2873 from whitequark/cxxrtl-fix-2500 whitequark 2021-07-16 11:01:10 +00:00
  • 37f5ed9439 Merge pull request #2872 from whitequark/cxxrtl-fix-2521 whitequark 2021-07-16 10:34:30 +00:00
  • 5b003d6e5c cxxrtl: run hierarchy pass regardless of (*top*) attribute presence. whitequark 2021-07-16 10:27:47 +00:00
  • 09218896d6 cxxrtl: emit debug items for unused public wires. whitequark 2021-07-16 10:05:24 +00:00
  • b28ca7f5ac cxxrtl: don't expect user cell inputs to be wires. whitequark 2021-07-16 09:51:15 +00:00
  • 10c3214e56 Merge pull request #2871 from whitequark/cxxrtl-fix-2540-2841 whitequark 2021-07-16 08:33:30 +00:00
  • 44a3d924ce cxxrtl: don't mark buffered internal wires as UNUSED for debug. whitequark 2021-07-16 07:36:18 +00:00
  • c17e385e35 Merge pull request #2870 from whitequark/cxxrtl-fix-2739 whitequark 2021-07-16 00:13:16 +00:00
  • 54b6cb645f cxxrtl: mark dead local wires as unused even with inlining disabled. whitequark 2021-07-15 22:27:27 +00:00
  • a9c8ca21d5 sv: fix two struct access bugs Zachary Snow 2021-06-22 10:39:57 -04:00
  • 1aab608cff Add a test for interfaces on modules loaded on-demand Rupert Swarbrick 2021-07-14 17:27:13 +01:00
  • 7d50b83322 Extract missing module support in hierarchy.cc to a helper function Rupert Swarbrick 2020-05-27 10:42:37 +01:00
  • 9008b87c39 Merge pull request #2866 from rswarbrick/found-init whitequark 2021-07-14 12:00:30 +00:00
  • 88f20fa4dd Delete unused found_init variable Rupert Swarbrick 2021-07-14 10:19:07 +01:00
  • 8bf9cb407d kernel/mem: Add a coalesce_inits helper. Marcelina Kościelnicka 2021-07-12 20:04:59 +02:00
  • 4379375d89 Add support for the Bitwuzla solver GCHQDeveloper560 2021-06-16 13:19:43 +01:00