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Mono Color

• f346868ccc flatten: Keep sigmap around between flatten_cell invocations. Marcelina Kościelnicka 2021-11-02 12:38:28 +01:00
• 9cb5092ad1 Bump version github-actions[bot] 2021-11-02 00:56:31 +00:00
• 5b834d3aff Merge pull request #3068 from YosysHQ/claire/verific_cfg Claire Xen 2021-11-01 12:53:47 +01:00
• 2ea757da51 Add "verific -cfg" command Claire Xenia Wolf 2021-11-01 10:41:51 +01:00
• 97fce665c7 Bump version github-actions[bot] 2021-11-01 01:05:04 +00:00
• e1cfd37384 ci: removed the old test.yml workflow, as it was replaced by test-linux.yml and test-macos.yml Aki Van Ness 2021-10-28 03:23:03 -04:00
• 1e7ba922e5 ci: expanded the macOS tests suite to cover more compilers and C++ versions Aki Van Ness 2021-10-27 21:43:51 -04:00
• ff31af6d72 ci: expanded the Linux test suite to cover more compilers and C++ versions Aki Van Ness 2021-10-27 19:18:16 -04:00
• ad81cff823 Changed the Makefile to have an explicit CXXSTD parameter which allows for the setting of other C++ standards, the default is c++11 Aki Van Ness 2021-10-27 20:02:33 -04:00
• dd06d23649 Merge pull request #3066 from YosysHQ/claire/verific_gclk Claire Xen 2021-10-31 18:04:54 +01:00
• 83118bfb9e Fix verific gclk handling for async-load FFs Claire Xenia Wolf 2021-10-31 17:12:29 +01:00
• dcb7096b5a Bump version github-actions[bot] 2021-10-30 00:51:07 +00:00
• c0edfa8788 Add missing items in CHANGELOG Miodrag Milanovic 2021-10-29 13:31:41 +02:00
• 55f07fe56f Update command reference part of manual Miodrag Milanovic 2021-10-29 13:10:50 +02:00
• 5f00bf2d7d Bump version github-actions[bot] 2021-10-28 00:52:35 +00:00
• 19c2d6e15d Merge pull request #3063 from YosysHQ/micko/verific_aldff Miodrag Milanović 2021-10-27 17:20:31 +02:00
• e14302a3ea ecp5: Add support for mapping aldff. Marcelina Kościelnicka 2021-10-27 14:04:21 +02:00
• f7cc388bb5 Enable async load dff emit by default in Verific Miodrag Milanovic 2021-10-27 15:56:56 +02:00
• 32673edfea Revert "Compile option for enabling async load verific support" Miodrag Milanovic 2021-10-27 15:55:43 +02:00
• 8d881826eb proc_dff: Emit $aldff. Marcelina Kościelnicka 2021-10-02 02:34:13 +02:00
• 0b31cb598e dfflegalize: Add tests for aldff lowering. Marcelina Kościelnicka 2021-10-27 13:37:26 +02:00
• 54c79af64f dfflegalize: Add tests targetting aldff. Marcelina Kościelnicka 2021-10-27 13:14:34 +02:00
• 0a0df8d38c dfflegalize: Refactor, add aldff support. Marcelina Kościelnicka 2021-10-27 10:14:07 +02:00
• bdf153d06c Bump version github-actions[bot] 2021-10-27 00:51:44 +00:00
• e833c6a418 verilog: use derived module info to elaborate cell connections Zachary Snow 2021-10-19 18:46:26 -06:00
• bd16d01c0e Split out logic for reprocessing an AstModule Rupert Swarbrick 2021-10-19 18:43:30 -06:00
• ee230f2bb9 Bump version github-actions[bot] 2021-10-26 00:51:59 +00:00
• b8624ad2ae Compile option for enabling async load verific support Miodrag Milanovic 2021-10-25 09:04:43 +02:00
• 52ba31b1c0 Bump version github-actions[bot] 2021-10-22 01:00:39 +00:00
• 5cebf6a8ef Change implicit conversions from bool to Sig* to explicit. Marcelina Kościelnicka 2021-10-21 18:26:47 +02:00
• 51d42cc917 Merge pull request #3057 from YosysHQ/claire/verific_latches Claire Xen 2021-10-21 13:00:53 +02:00
• 90b440f870 Fix verific.cc PRIM_DLATCH handling Claire Xenia Wolf 2021-10-21 12:13:35 +02:00
• 16a177560f Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS} Claire Xenia Wolf 2021-10-21 05:42:47 +02:00
• e64456f920 extract_reduce: Refactor and fix input signal construction. Marcelina Kościelnicka 2021-10-21 02:58:10 +02:00
• a0e9d9fef9 Bump version github-actions[bot] 2021-10-21 00:59:29 +00:00
• 25c4ed3beb Fix emcc warnings for WebAssembly build Daniel Huisman 2021-10-20 14:43:30 +02:00
• bf79ff5927 If verific have vhdl lib it is required by other libs Miodrag Milanovic 2021-10-20 13:08:08 +02:00
• 150ce305f9 Forgot to remove from main list Miodrag Milanovic 2021-10-20 12:37:22 +02:00
• 17269ae59b Option to disable verific VHDL support Miodrag Milanovic 2021-10-20 10:02:58 +02:00
• 69b2b13ddd Bump version github-actions[bot] 2021-10-20 00:56:49 +00:00
• fe9689c136 Fixed Verific parser error in ice40 cell library Claire Xenia Wolf 2021-10-19 12:33:01 +02:00
• affed103e0 Merge pull request #3045 from galibert/master Miodrag Milanović 2021-10-19 11:23:57 +02:00
• 83887495b8 Fixes in vcdcd.pl for newer Perl versions Claire Xenia Wolf 2021-10-19 10:56:43 +02:00
• a15b01a777 Bump version github-actions[bot] 2021-10-18 00:56:23 +00:00
• 3efc14f5ad dfflegalize: remove redundant check for initialized dlatch Paul Annesley 2021-10-17 12:56:32 +11:00
• 6e78a80ff9 CycloneV: Add (passthrough) support for cyclonev_oscillator Olivier Galibert 2021-10-17 20:00:03 +02:00
• 6253d4ec9e CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose Olivier Galibert 2021-10-14 16:56:10 +02:00
• 0dd42d406d Bump version github-actions[bot] 2021-10-16 00:58:22 +00:00
• 92ecfb2b36 Merge pull request #3044 from YosysHQ/micko/verific_bufif1 Claire Xen 2021-10-15 16:43:25 +02:00
• 1aa6896966 Support PRIM_BUFIF1 primitive Miodrag Milanovic 2021-10-14 13:04:32 +02:00
• a0f5ba8501 Bump version github-actions[bot] 2021-10-12 00:57:44 +00:00
• 2d3c79458d Merge pull request #3039 from YosysHQ/claire/verific_aldff Claire Xen 2021-10-11 10:01:56 +02:00
• c8074769b0 Add Verific adffe/dffsre/aldffe FIXMEs Claire Xenia Wolf 2021-10-11 10:00:20 +02:00
• d5cc3a1c72 Merge pull request #3040 from YosysHQ/micko/split_module_ports Claire Xen 2021-10-11 09:56:05 +02:00
• c15b99c0de Merge pull request #3041 from YosysHQ/mmicko/module_attr Claire Xen 2021-10-11 09:54:28 +02:00
• 93fbc9fba4 Import module attributes from Verific Miodrag Milanovic 2021-10-10 10:01:45 +02:00
• ff8e999a71 Split module ports, 20 per line Miodrag Milanovic 2021-10-09 13:40:55 +02:00
• d8f6d7b18d Bump version github-actions[bot] 2021-10-09 00:51:28 +00:00
• 34f1df8435 Fixes and add comments for open FIXME items Claire Xenia Wolf 2021-10-08 17:24:45 +02:00
• 1602a03864 Add support for $aldff flip-flops to verific importer Claire Xenia Wolf 2021-10-08 16:21:25 +02:00
• dc8da76282 Fix a regression from #3035. Marcelina Kościelnicka 2021-10-08 14:51:57 +02:00
• 772b9a108a Bump version github-actions[bot] 2021-10-08 00:57:28 +00:00
• 4e70c30775 FfData: some refactoring. Marcelina Kościelnicka 2021-10-06 22:16:55 +02:00
• 356ec7bb39 Bump version github-actions[bot] 2021-10-05 00:53:24 +00:00
• abc5700628 verific set db_infer_set_reset_registers Miodrag Milanovic 2021-10-04 16:48:33 +02:00
• f3ef579ac4 Bump version github-actions[bot] 2021-10-03 00:58:23 +00:00
• e7d89e653c Hook up $aldff support in various passes. Marcelina Kościelnicka 2021-10-02 01:23:43 +02:00
• ba0723cad7 zinit: Refactor to use FfData. Marcelina Kościelnicka 2021-10-02 00:05:22 +02:00
• 63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load. Marcelina Kościelnicka 2021-10-01 23:50:48 +02:00
• ec2b5548fe Add $aldff and $aldffe: flip-flops with async load. Marcelina Kościelnicka 2021-10-01 04:33:00 +02:00
• fbd70f28f0 Specify minimum bison version 3.0+ Zachary Snow 2021-10-01 14:41:11 -06:00
• f9aad606ca simplemap: refactor to use FfData. Marcelina Kościelnicka 2021-10-02 00:42:36 +02:00
• 62739f7bf7 Merge pull request #3017 from YosysHQ/claire/short_rtlil_x_const Miodrag Milanović 2021-09-28 18:03:14 +02:00
• 7a7df9a3b4 Bump version github-actions[bot] 2021-09-28 00:53:49 +00:00
• 070cad5f4b Prepare for next release cycle Miodrag Milanovic 2021-09-27 16:24:43 +02:00
• dca8fb54aa Yosys x.y.z yosys-0.10 Claire Xenia Wolf 2021-09-27 16:07:30 +02:00
• 89df26e4bc Add optimization to rtlil back-end for all-x parameter values Claire Xenia Wolf 2021-09-27 16:02:20 +02:00
• 1cac671c70 Bump version github-actions[bot] 2021-09-25 00:51:53 +00:00
• 0146d83ed8 Merge pull request #3014 from YosysHQ/claire/fix-vgtest Claire Xen 2021-09-24 17:50:34 +02:00
• 9658d2e337 Fix TOK_ID memory leak in for_initialization Zachary Snow 2021-09-23 13:33:55 -04:00
• 15fb0107dc Fix "make vgtest" so it runs to the end (but now it fails ;) Claire Xenia Wolf 2021-09-22 17:34:20 +02:00
• 9432400ec8 Bump version github-actions[bot] 2021-09-22 00:54:54 +00:00
• d6fe6d4fb6 sv: support wand and wor of data types Zachary Snow 2021-08-13 20:51:28 -07:00
• 6b7267b849 verilog: fix multiple AST_PREFIX scope resolution issues Zachary Snow 2021-08-02 18:42:34 -06:00
• 3931b3a03f Bump version github-actions[bot] 2021-09-19 00:52:56 +00:00
• 1362ad0bf8 Update WaveDrom script URLs Daniel Huisman 2021-09-18 16:24:40 +02:00
• e6766b950c Merge pull request #3010 from the6p4c/master Miodrag Milanović 2021-09-18 09:16:58 +02:00
• c25122e339 Fix protobuf backend build dependencies the6p4c 2021-09-17 13:36:37 +10:00
• c88eaea6e0 Bump version github-actions[bot] 2021-09-14 00:56:06 +00:00
• 551ef85cd7 verilog: Squash flex-triggered warning. Marcelina Kościelnicka 2021-09-13 15:38:54 +02:00
• 1d52c07e9b Updates for CHANGELOG (#2997) Miodrag Milanović 2021-09-13 16:25:42 +02:00
• f44110c625 Bump version github-actions[bot] 2021-09-11 00:50:11 +00:00
• 396918cc30 Merge pull request #3001 from YosysHQ/claire/sigcheck Miodrag Milanović 2021-09-10 17:32:04 +02:00
• 4708907be8 Add additional check to SigSpec Claire Xenia Wolf 2021-09-10 16:51:34 +02:00
• 33749f1e3a yosys-smtbmc: Fix reused loop variable. Marcelina Kościelnicka 2021-09-10 04:55:48 +02:00
• 1d61a911b7 Bump version github-actions[bot] 2021-09-10 00:55:14 +00:00
• 96b6410dcb abc9: make re-entrant (#2993) Eddie Hung 2021-09-09 10:06:31 -07:00
• 65316ec926 abc9: holes module to instantiate cells with NEW_ID (#2992) Eddie Hung 2021-09-09 10:06:20 -07:00
• f03e2c30aa abc9: replace cell type/parameters if derived type already processed (#2991) Eddie Hung 2021-09-09 10:05:55 -07:00
• 50be8fd0c2 Bump version github-actions[bot] 2021-09-03 00:50:30 +00:00