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Commit Graph

6 Commits

Author SHA1 Message Date
Anton Blanchard
5a7fcbc814 Add Colorlight 5A-75B support
This adds support for the cheap Colorlight 5A-75B ECP5 based board.

UART RX is on J19, labelled key+ on the silk screen on the back
UART TX is on J1, pin 1.

All the I/Os on this board go through bidirectional level shifters that
appear to be hardwired as outputs. To get an input pin for UART RX, we
use the button I/O which is also routed to connector J19. The downside is
we can't use the button for reset.

One potential issue is that UART TX is 5V but UART RX is 3.3V. To keep
the FPGA happy any attached UART chip needs to output 3.3V, but it also
needs to be 5V tolerant to handle the level shifted input.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-20 11:48:08 +11:00
Anton Blanchard
8293ade696 Need reg on pll_bypass.v outputs
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-03 10:37:00 +11:00
Anton Blanchard
c942fba2a9 Reformat PLLs
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
d2e04d01ff Add pll_bypass.v
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
43e1e73ce8 Rename PLL
Now we have multiple PLLs it makes no sense to call it pll_ecp5_evn.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
d0a15b35de Move PLLs into pll/
Also rename pll_ecp5_evn.v to pll_ehxplll.v

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00