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Author SHA1 Message Date
Anton Blanchard
bd1ec9c7ce
Merge pull request #19 from edwardcwang/mill 
Add support for mill
 2020-02-22 11:58:23 +11:00
Anton Blanchard
473f1b2008
Merge pull request #20 from antonblanchard/colorlight 
Add Colorlight 5A-75B support
 2020-02-20 14:20:58 +11:00
Anton Blanchard
5a7fcbc814 Add Colorlight 5A-75B support 
This adds support for the cheap Colorlight 5A-75B ECP5 based board.

UART RX is on J19, labelled key+ on the silk screen on the back
UART TX is on J1, pin 1.

All the I/Os on this board go through bidirectional level shifters that
appear to be hardwired as outputs. To get an input pin for UART RX, we
use the button I/O which is also routed to connector J19. The downside is
we can't use the button for reset.

One potential issue is that UART TX is 5V but UART RX is 3.3V. To keep
the FPGA happy any attached UART chip needs to output 3.3V, but it also
needs to be 5V tolerant to handle the level shifted input.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-20 11:48:08 +11:00
Edward Wang
db7736a92b Add test_run_dir to gitignore 
Signed-off-by: Edward Wang <edward.c.wang@compdigitec.com>
 2020-02-10 23:45:26 -05:00
Edward Wang
d4a55ffdfe Add support for mill 
Signed-off-by: Edward Wang <edward.c.wang@compdigitec.com>
 2020-02-10 23:45:26 -05:00
Anton Blanchard
8ddfc34a48
Merge pull request #18 from antonblanchard/fix-travis 
Fix make check and Travis CI
 2020-02-08 23:29:26 +11:00
Anton Blanchard
35b7c9a054 Fix make check and Travis CI 
We weren't propagating all errors back to Travis CI, so make check wasn't
actually being tested.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-08 23:14:13 +11:00
Anton Blanchard
d575c18cfb
Merge pull request #17 from antonblanchard/fix-multiply 
Fix multiply
 2020-02-08 23:12:05 +11:00
Anton Blanchard
dc8b74d51d Improve Multiplier tests 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-08 23:01:44 +11:00
Anton Blanchard
8cd001568a Fix signed multiply 
The upper bits of signed multiplications was all wrong. Fix it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-08 14:36:52 +11:00
Anton Blanchard
1a98f5af27
Merge pull request #16 from antonblanchard/README-updates 
More updates to the README
 2020-02-06 22:25:03 +11:00
Anton Blanchard
55df763dc5 More updates to the README 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-06 22:21:51 +11:00
Anton Blanchard
03af00c480
Merge pull request #15 from antonblanchard/rework-slowops 
Rework slowops
 2020-02-06 22:19:41 +11:00
Anton Blanchard
afbf03c51f
Merge pull request #13 from antonblanchard/rework-loadstore 
Rework load/store to improve timing
 2020-02-06 22:03:13 +11:00
Anton Blanchard
8cf5edf237
Merge pull request #14 from antonblanchard/printf-formatting 
Add CR to printfs
 2020-02-06 22:02:54 +11:00
Anton Blanchard
9fb5b93c69 Buffer multiplier final formatting 
Also remove a side channel easter egg.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-06 21:52:50 +11:00
Anton Blanchard
4ebe7adf28 Buffer divide final formatting 
Add an extra cycle to the divider that buffers the final formatting.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-06 21:50:23 +11:00
Anton Blanchard
80d8e3a2cb Add CR to printfs 
Since we are in raw mode, LR doesn't get converted into CR/LF.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-06 21:40:41 +11:00
Anton Blanchard
e770a35a0e Rework load/store to improve timing 
By moving the load from the second cycle into the first cycle we improve
timing overall.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-06 21:36:50 +11:00
Anton Blanchard
cdb995c6e1
Merge pull request #12 from antonblanchard/fusesoc-nexys-video 
FuseSoC Nexys Video support
 2020-02-06 21:30:00 +11:00
Anton Blanchard
ca3e38c194 FuseSoC Nexys Video support 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-06 21:13:06 +11:00
Anton Blanchard
94233ed756
Merge pull request #11 from antonblanchard/ram-timing 
Improve memory read timing by removing readData signals
 2020-02-06 21:11:41 +11:00
Anton Blanchard
4dc5f030e0 Improve memory read timing by removing readData signals 
There's no need to gate reads.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-05 12:06:17 +11:00
Anton Blanchard
08fd7fc02b
Merge pull request #10 from antonblanchard/pipeline-cleanup 
Fix some timing issues in writeback
 2020-02-04 08:56:54 +11:00
Anton Blanchard
be6e0cae22 Fix some timing issues in writeback 
Break the writeback mux into two chunks so that all units that have RC
instructions mux into an intermediate signal wrRcData. This gets fed into
the compare logic.

Compare instructions are all fed through the Adder, so use the adder
output instead of the writeback mux.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-04 08:00:42 +11:00
Anton Blanchard
7d5338dd5f
Merge pull request #9 from antonblanchard/reset-fix 
Temporary reset fix
 2020-02-03 13:17:58 +11:00
Anton Blanchard
842c9cebd4
Merge pull request #8 from antonblanchard/arty 
FuseSoC Arty A7 support
 2020-02-03 13:06:45 +11:00
Anton Blanchard
fb60b534b2 Temporary reset fix 
We need to clean up the nia/fetch handling, but avoid the situation
where we come out of reset right around the time completed goes high.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-03 13:00:17 +11:00
Anton Blanchard
f272e0ff16 Add FuseSoC Arty A7 support 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-03 10:40:05 +11:00
Anton Blanchard
6521f39829 Rearrange cmod_a7-35.xdc 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-03 10:37:47 +11:00
Anton Blanchard
8293ade696 Need reg on pll_bypass.v outputs 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-03 10:37:00 +11:00
Anton Blanchard
c4ac79c1d7
Merge pull request #7 from antonblanchard/makefile-cleanup 
Makefile: Add PLL variable
 2020-02-02 21:46:45 +11:00
Anton Blanchard
7fe392d06b Makefile: Add PLL variable 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-02 14:25:43 +11:00
Anton Blanchard
5abdf7ce5c
Merge pull request #6 from antonblanchard/fusesoc 
FuseSoC Support
 2020-02-02 14:24:30 +11:00
Anton Blanchard
ae8466e8de Reformat toplevel.v 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-02 14:03:00 +11:00
Anton Blanchard
c942fba2a9 Reformat PLLs 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-02 14:03:00 +11:00
Anton Blanchard
d2e04d01ff Add pll_bypass.v 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-02 14:03:00 +11:00
Anton Blanchard
43e1e73ce8 Rename PLL 
Now we have multiple PLLs it makes no sense to call it pll_ecp5_evn.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-02 14:03:00 +11:00
Anton Blanchard
d0a15b35de Move PLLs into pll/ 
Also rename pll_ecp5_evn.v to pll_ehxplll.v

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-02 14:03:00 +11:00
Anton Blanchard
e3990af2ef Add FuseSoC support 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-02 14:03:00 +11:00
Anton Blanchard
df3a74798e Add a parameter to control the polarity of reset 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-02-02 09:02:33 +11:00
Anton Blanchard
fb166bbfae
Merge pull request #4 from antonblanchard/orange-crab-reset 
Invert OrangeCrab reset
 2020-01-31 08:26:27 +11:00
Anton Blanchard
843749403f Invert OrangeCrab reset 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-31 08:15:34 +11:00
Anton Blanchard
b44faeb038
Merge pull request #3 from antonblanchard/micropython-test 
Add a micropython test
 2020-01-31 06:43:58 +11:00
Anton Blanchard
8f8382a2a9 Add a micropython test 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-31 06:33:40 +11:00
Anton Blanchard
df8ee8b4fb
Merge pull request #2 from antonblanchard/travis 
Initial Travis CI file
 2020-01-31 05:34:11 +11:00
Anton Blanchard
ebce5ccedb Initial Travis CI file 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-31 05:19:39 +11:00
Anton Blanchard
593c183c8c Fix some compiler warnings in uart.c 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-31 05:14:44 +11:00
Anton Blanchard
63ed617cb6 Remove SystemVerilog syntax 
Lattice Diamond doesn't seem to support SystemVerilog which is a bit
depressing. We only use the syntax in a few places, so fix that up.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-31 02:49:26 +11:00
Anton Blanchard
1aeb5dad28 Remove an unused bit from the Divider 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-30 18:23:01 +11:00