18 Commits

Author	SHA1	Message	Date
J	f16479b668	some more instruction colation	2019-09-26 21:15:44 -04:00
JnR	ff3e286289	Start to simplify the staircase decoder	2019-09-25 22:19:31 -04:00
J	e661848e58	Change back to complete ROM tests. NOTE: may overflow FPGA	2019-09-22 23:06:25 -04:00
J	3ca89bdbd0	Remove hack to work around incomplete pipeline reset due to Lattice tools, fixed by reset generator	2019-04-02 21:11:55 -04:00
J	5825a157cf	Cosmetic... print key names. RAM full, use rev 28 for block ram checking instead	2019-04-01 17:45:50 -04:00
J	6acf3a811c	All keys work. First 'scan' algorithm. Precharge timing needs tuning	2019-03-31 02:10:36 -04:00
J	e14eca18c0	CPU comes up. Lattice SPR works. LCD works.	2019-03-30 17:21:02 -04:00
J	3ec7c27f36	Continue simple cleanups of pinouts and platform split. Still doesn't work, though	2019-03-27 21:04:53 -04:00
J	d21f78598e	With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.	2019-03-25 21:50:49 -04:00
J	f7ad4be38a	Finish Free42 pinout. First synth with all pins. Seems to break LCD?	2019-03-19 16:44:01 -04:00
J	07afa61fa1	Drives LCD with ASCII renderer. Split main.c off for 42s	2019-03-18 17:39:56 -04:00
J	2246a52244	Work around strange %pr bug in entry.c. Finally runs to C code	2019-03-17 17:03:19 -04:00
J	c611736bad	Sync RAM register file implemntation	2019-03-13 17:05:56 -04:00
J	fb8fdd41c7	move back to ghdl because nvc can't trace records yet, even though it simulates them	2019-03-12 22:42:41 -04:00
J	93d011ba48	Add sim by default and wave viewer ctl file for reg file debug	2019-03-08 01:37:20 -05:00
J	dfd7c38c98	Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk	2019-03-08 01:09:52 -05:00
J	f0dbd0a33e	correct outputs for Lattice EVB. Fix stack location. Still crashes with result code 0x11 on the LEDs	2019-03-05 02:17:06 -05:00
J	b1176ec9aa	First synthesys for ICE40 UP5k with everything to blink LEDs	2019-03-04 01:17:33 -05:00