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J 93d011ba48 Add sim by default and wave viewer ctl file for reg file debug
2019-03-08 01:37:20 -05:00
testrom
correct outputs for Lattice EVB. Fix stack location. Still crashes with result code 0x11 on the LEDs
2019-03-05 02:17:06 -05:00
asymmetric_ram.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
bus_monitor.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
clk_sim.vhd
Actually add sim model for Lattice HF clk
2019-03-08 01:10:20 -05:00
components_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
conv.c
First synthesys for ICE40 UP5k with everything to blink LEDs
2019-03-04 01:17:33 -05:00
cpu2j0_pkg.vhd
Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used
2019-03-03 17:29:03 -05:00
cpu_lattice.vhd
Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk
2019-03-08 01:09:52 -05:00
cpu_pure_tb.vhh
With single port RAM
2019-03-03 23:16:35 -05:00
cpu_simple_sram.vhd
With single port RAM
2019-03-03 23:16:35 -05:00
cpu_sram.vhd
Add testrom, modified for small memory... enable tests if you need in Makefile
2019-03-03 20:55:24 -05:00
cpu.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
data_bus_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
datapath_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
datapath.vhd
Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used
2019-03-03 17:29:03 -05:00
decode_body.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
decode_core.vhd
Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used
2019-03-03 17:29:03 -05:00
decode_pkg.vhd
Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used
2019-03-03 17:29:03 -05:00
decode_table_reverse.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
decode_table.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
decode.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
ghdl.sh
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
lattice_ebr.vhd
First synthesys for ICE40 UP5k with everything to blink LEDs
2019-03-04 01:17:33 -05:00
lattice_tb.vhd
Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk
2019-03-08 01:09:52 -05:00
monitor_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
mult_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
mult.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
nvc_lattice.sh
Add sim by default and wave viewer ctl file for reg file debug
2019-03-08 01:37:20 -05:00
nvc_simple.sh
With single port RAM
2019-03-03 23:16:35 -05:00
nvc.sh
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
ram_init.vhd
Add sim by default and wave viewer ctl file for reg file debug
2019-03-08 01:37:20 -05:00
ram.img
Add sim by default and wave viewer ctl file for reg file debug
2019-03-08 01:37:20 -05:00
ram.sh
First synthesys for ICE40 UP5k with everything to blink LEDs
2019-03-04 01:17:33 -05:00
reg.gtkw
Add sim by default and wave viewer ctl file for reg file debug
2019-03-08 01:37:20 -05:00
register_file.vhd
Regfile now uses sync ram, -ve clock read. Generics have defaults
2019-03-03 16:28:34 -05:00
simple_ram.vhd
With single port RAM
2019-03-03 23:16:35 -05:00
timeout_cnt.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
up5k.pcf
Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk
2019-03-08 01:09:52 -05:00
verific
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
Description
J-core SOC for ice40 FPGA
379 KiB
Languages
VHDL 75.2%
Assembly 14.1%
C 9.3%
Shell 0.8%
Linker Script 0.3%
Other 0.3%