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Author SHA1 Message Date
Joerg Hoppe
f314317e2a DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP 2019-10-04 12:45:26 +02:00
Joerg Hoppe
73b9d2f9fb Better integration of CPU20 into UniBone framework 2019-09-26 07:54:19 +02:00
Joerg Hoppe
cef911f70b Better integration of CPU20 into UniBone framework 2019-09-26 07:42:59 +02:00
Joerg Hoppe
43f567024a Successful INTR on emulated CPU20 with emulated DL11 2019-09-24 14:33:41 +02:00
Joerg Hoppe
b2d944f9cd First successful iNTR on emulated CPU20 2019-09-23 13:42:47 +02:00
Joerg Hoppe
47bf827c52 typo 2019-09-19 14:06:06 +02:00
Joerg Hoppe
3c011252ab Reworked inputline() 2019-09-19 13:09:05 +02:00
Joerg Hoppe
07e8e2a96e removed --debug from .sh-scripts 2019-09-19 13:07:27 +02:00
Joerg Hoppe
9089ee06b6 Reworked inputline() 2019-09-19 13:02:11 +02:00
Joerg Hoppe
bf6d60363c Reworked inputline() 2019-09-19 13:01:31 +02:00
Joerg Hoppe
b9d28d73c4 Start MSCP test, KW11 without "line monitor bit clear" 2019-09-19 12:58:38 +02:00
Joerg Hoppe
5812d82651 increased max DMA chunk size from 512 to 4K (test, and RAM was free) 2019-09-19 12:56:52 +02:00
Joerg Hoppe
e46b26b497 DL11 / KW11 ZDLD and RSX11 OK 2019-09-19 10:56:43 +02:00
Joerg Hoppe
e102425ebe 32/64 problem, no timeouts > 4.2 secs were possible. 2019-09-05 10:25:32 +02:00
Joerg Hoppe
92714c1ebe Test "MultiArb": parallel INTR and DMA of DL11,RL11,RK11. 
Also MSCP IOX.
 2019-09-02 15:46:54 +02:00
Joerg Hoppe
cc42d60409 type in dir name 2019-09-02 15:37:29 +02:00
Joerg Hoppe
15d22c8e25 /home/joerg/retrocmp/dec/UniBone/workspace 2019-09-01 06:47:30 +02:00
Joerg Hoppe
f13b35bc08 KW11 LKS line monitor bit can only be cleared 2019-08-31 17:29:48 +02:00
Joerg Hoppe
30df58f42c fix baudrate bit width 2019-08-30 13:38:34 +02:00
Joerg Hoppe
e3ca35f24b device parameter interurpt vector&level not udpated 2019-08-28 16:45:52 +02:00
Joerg Hoppe
52d646973d delay after powercycle, so system is stable for next operation 2019-08-28 16:45:08 +02:00
Joerg Hoppe
d058310e53 CPU20 power start/power fail 2019-08-27 19:05:41 +02:00
Joerg Hoppe
6f2adbd216 levelchange(PSW) on RTI 2019-08-27 13:31:37 +02:00
Joerg Hoppe
827515eb8c module rename for upcoming intr_slave 2019-08-26 13:51:34 +02:00
Joerg Hoppe
ea91180f28 Connected CPU20 to INTR,INIT,Power ON/OFF. 
PRU INTR routing still do to.
 2019-08-25 09:17:28 +02:00
Joerg Hoppe
f938c8ba8a Power OFF event now from ACLO 
PRU bugfix: if DMA cycle started by register access cycle
Extended interface for emulated CPU
 2019-08-22 17:30:21 +02:00
Joerg Hoppe
fa454f646c added listing for easy loading 2019-08-19 13:26:22 +02:00
Joerg Hoppe
3d1d9d3cf6 ACLO/DCLO/INIT moved from PRU to ARM 
INTR/DMA request params linked to device params on change
 2019-08-19 13:12:42 +02:00
Joerg Hoppe
e2229871de PDP-11 test program for concurrent INTR/DMA 
Serial, Clock, RL02, RK05, MSCP
 2019-08-19 12:57:18 +02:00
Joerg Hoppe
8ff33a0be1 Infrastructure for emulated CPUs: Bus arbitrator, Interrupt fielding processor 2019-08-16 19:04:12 +02:00
Jörg Hoppe
155b02a089 Merge pull request #3 from livingcomputermuseum/master 
Fixes for MSCP with new DMA/IRQ infrastructure
 2019-08-16 14:25:44 +02:00
Josh Dersch
6f1b476716 Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait). 
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes
with latest PRU code -- MSCP works reliably on PDP-11/84 again.
 2019-08-16 02:23:32 +02:00
Josh Dersch
073a2334b6 Fixes for MSCP after Joerg's INTR/DMA rewrites: 
- Fixed programmable interrupt vector (was broken after changes)
- Fixed interrupts during MSCP 4-stage init to atomically update SA register; 4.3bsd now boots.
 2019-08-14 09:46:32 +02:00
Josh Dersch
1d4fe694ae Merge remote-tracking branch 'upstream/master' 2019-08-12 17:28:19 -07:00
Joerg Hoppe
7eaa7c0729 RL11 changed to atomically INTR/CSR write. Passes exerciser ZRLKB3 now for 2h. 2019-08-12 12:21:56 +02:00
Joerg Hoppe
5ba6142b52 cleanup 2019-08-10 12:10:44 +02:00
Joerg Hoppe
39caffd6e6 Emulated DL11: stream interface parallel to RS232. 
demo: "dl11 rcv" and "dl11 wait" script extension
cleanup
 2019-08-10 10:19:05 +02:00
Joerg Hoppe
313957631f Cleanup, fixes Interrupt logic, RL11 tests 2019-08-08 07:32:08 +02:00
Joerg Hoppe
855f1a6cee GitHub usability 2019-08-05 09:28:07 +02:00
Joerg Hoppe
d9b49ac70f Fix GitHub repository 2019-08-05 08:37:03 +02:00
Joerg Hoppe
10cf1598f1 Big summer rework: 
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
 2019-08-02 20:10:48 +02:00
Joerg Hoppe
974aeed8eb Big summer rework: 
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
 2019-08-02 16:45:54 +02:00
Joerg Hoppe
471df2d8ea PRU1: multiple parallel timeouts 2019-07-03 21:48:49 +02:00
Joerg Hoppe
3f783e5000 Missing source added 2019-07-02 13:02:06 +02:00
Joerg Hoppe
04869fb46f PRU statemachines easier to control from main thread 2019-07-02 07:09:01 +02:00
Joerg Hoppe
e23b2cf4d3 Dl11w rcv intr 2019-06-26 07:48:31 +02:00
Joerg Hoppe
01efdee04a DL11W interrupt tests&fixes 2019-06-25 16:47:17 +02:00
Joerg Hoppe
81c3295e31 DL11 cleanup&fixes 2019-06-24 17:25:20 +02:00
Joerg Hoppe
28ab69050c break enable, maintenance loopback 2019-06-24 14:51:18 +02:00
Joerg Hoppe
b749ce5897 SLU compiles, minimal function 2019-06-24 12:03:47 +02:00