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Author	SHA1	Message	Date
Olof Kindgren	8ae05ea4cf	Rewrite immediate decoder	2018-12-25 13:13:04 +01:00
Olof Kindgren	78821c16b3	Optimize op_b selector	2018-12-25 13:13:04 +01:00
Olof Kindgren	e3e616903e	Optimize bool operations	2018-12-25 13:13:04 +01:00
Olof Kindgren	1d04ed9c50	Fix errors in core file	2018-12-16 08:48:48 +01:00
Olof Kindgren	4a224fc985	Fix failing compliance tests	2018-12-13 12:03:42 +01:00
Olof Kindgren	3f5c25d8f2	Silence LSE warnings	2018-12-12 21:20:44 +01:00
Olof Kindgren	09bb05071e	Fix bugs and missing resets to pass formal	2018-12-11 22:05:32 +01:00
Olof Kindgren	af1d4da8bf	Fix rvfi logic	2018-12-11 22:02:03 +01:00
Olof Kindgren	f52eb1931d	Add info about some of serv's shortcomings	2018-12-08 00:16:35 +01:00
Olof Kindgren	f627aee1a1	Syntax fixes to please Vivado	2018-12-07 23:20:47 +01:00
Olof Kindgren	468e99ac7c	Syntax fixes to please Quartus	2018-12-07 22:55:55 +01:00
Olof Kindgren	6cd3d2d3ef	Fix rvfi_insn	2018-12-06 23:47:52 +01:00
Olof Kindgren	836a013462	Fix clock generation	2018-12-06 22:12:03 +01:00
Olof Kindgren	b569d08d02	Update documentation	2018-12-05 19:36:14 +01:00
Olof Kindgren	fc82862e96	Add icepll generator and run tinyfpga BX at 32MHz	2018-12-03 12:26:17 +01:00
Olof Kindgren	16666c319e	Update zephyr submodule	2018-11-26 23:17:21 +01:00
Olof Kindgren	7fabafa9cf	Add sync example	2018-11-26 23:15:53 +01:00
Olof Kindgren	25791b10c2	Add memsize param to FPGA targets	2018-11-26 23:13:50 +01:00
Olof Kindgren	cd983190b3	Interrupts working. Adding philosophers example	2018-11-26 23:03:40 +01:00
Olof Kindgren	e1a883acc2	Add zephyr fork as submodule	2018-11-26 18:05:01 +01:00
Olof Kindgren	05640dfe30	Update README	2018-11-26 18:00:39 +01:00
Olof Kindgren	4649b7073f	Update example applications	2018-11-26 18:00:29 +01:00
Olof Kindgren	ec8252ea0a	Add memsize parameter	2018-11-26 17:54:10 +01:00
Olof Kindgren	11a2195146	First attempt att interrupt support	2018-11-26 16:01:07 +01:00
Olof Kindgren	12039dec0e	Add support for setting memory contents during synthesis	2018-11-26 09:49:08 +01:00
Olof Kindgren	e1f5bcc4f3	Rewrite register file	2018-11-26 00:09:52 +01:00
Olof Kindgren	a974320f46	Further optimizations	2018-11-23 21:26:49 +01:00
Olof Kindgren	b8f5133267	Random optimizations	2018-11-23 13:59:07 +01:00
Olof Kindgren	1bbf8e3ce9	Synthesis fixes	2018-11-22 20:58:45 +01:00
Olof Kindgren	458d12c81d	Remove dead code	2018-11-22 13:10:28 +01:00
Olof Kindgren	f2e1e4a52b	Add support for IceBreaker board	2018-11-22 13:03:23 +01:00
Olof Kindgren	fa8def6e7a	Rewrite immediate decoding	2018-11-22 13:02:51 +01:00
Olof Kindgren	94c7dab38d	Addapt compliance_test printing to new signature format	2018-11-22 13:00:27 +01:00
Olof Kindgren	47b2db20c3	Remove missing file from .core	2018-11-21 13:33:54 +01:00
Olof Kindgren	f15cab5458	Fix linter complaints	2018-11-21 13:25:37 +01:00
Olof Kindgren	079d973969	Cleanup	2018-11-21 13:22:55 +01:00
Olof Kindgren	9df2a0060b	Use custom interconnect. Runs on hw	2018-11-21 13:15:33 +01:00
Olof Kindgren	6e034361d4	Add UART decoder	2018-11-19 09:42:42 +01:00
Olof Kindgren	f7b396601f	Cleanup	2018-11-18 23:15:32 +01:00
Olof Kindgren	a1093451e5	Add draft README	2018-11-18 22:36:48 +01:00
Olof Kindgren	c2c162c2dd	Update after changes to riscv-compliance repo	2018-11-18 22:32:25 +01:00
Olof Kindgren	5db1864ba9	Add modified core dependencies	2018-11-18 22:31:53 +01:00
Olof Kindgren	530eaafdb9	Add riscv-target files	2018-11-18 21:48:30 +01:00
Olof Kindgren	ff63519607	Temporary hack to blink LED on tinyfpga BX	2018-11-18 21:42:42 +01:00
Olof Kindgren	2062d084bf	Disable GPIO output in verilator	2018-11-18 21:40:51 +01:00
Olof Kindgren	7666ac4092	synthesized netlist works	2018-11-18 13:05:38 +01:00
Olof Kindgren	d4102f927f	Synthesis fixes	2018-11-17 22:14:44 +01:00
Olof Kindgren	0362192769	Use internal reset	2018-11-17 22:06:10 +01:00
Olof Kindgren	f66f82a57a	Add explicit wire defs to ports	2018-11-17 21:30:03 +01:00
Olof Kindgren	0036756157	Pass compliance tests	2018-11-15 14:16:01 +01:00