22 Commits

Author	SHA1	Message	Date
Olof Kindgren	126937f16a	Rewrite RF and state machine ... Big patch, but would take more work to split it up	2019-09-26 23:09:22 +02:00
Olof Kindgren	31852f175d	Simplify alu_cmp_eq control logic	2019-07-23 12:10:38 +02:00
Olof Kindgren	af3b82f9ac	Optimize take_branch condition	2019-07-23 12:10:38 +02:00
Olof Kindgren	e107627e71	Reduce warnings	2019-06-24 15:22:08 +02:00
Olof Kindgren	bba836ad8c	Fix width mismatches to make code verilator clean	2019-03-25 20:57:13 +01:00
Olof Kindgren	6e91409990	Optimize alu eq check	2019-03-20 08:35:43 +01:00
Olof Kindgren	a550137453	Use bufreg for shifter	2019-03-20 08:35:43 +01:00
Olof Kindgren	f5a1590422	Remove duplicated adder+inverter	2019-01-10 18:15:20 +01:00
Olof Kindgren	e3e616903e	Optimize bool operations	2018-12-25 13:13:04 +01:00
Olof Kindgren	09bb05071e	Fix bugs and missing resets to pass formal	2018-12-11 22:05:32 +01:00
Olof Kindgren	1bbf8e3ce9	Synthesis fixes	2018-11-22 20:58:45 +01:00
Olof Kindgren	9df2a0060b	Use custom interconnect. Runs on hw	2018-11-21 13:15:33 +01:00
Olof Kindgren	f66f82a57a	Add explicit wire defs to ports	2018-11-17 21:30:03 +01:00
Olof Kindgren	cbbdaed112	slli, srli, add, sll, sltiu, slt, xor, srl, sra, or, and	2018-11-02 13:48:08 +01:00
Olof Kindgren	8409aa4c4b	lh, lw, lbu, lhu, sb, sh, slti	2018-11-01 22:51:51 +01:00
Olof Kindgren	c90920d9b2	bge, bltu, bgeu	2018-11-01 09:35:49 +01:00
Olof Kindgren	d4bbe17e78	jalr, blt	2018-10-31 14:51:28 +01:00
Olof Kindgren	d4b2697761	auipc, sub	2018-10-30 23:33:28 +01:00
Olof Kindgren	96b1906676	bne, srai	2018-10-30 22:41:05 +01:00
Olof Kindgren	66000a77f5	beq, sw	2018-10-28 23:54:04 +01:00
Olof Kindgren	c2030a95fd	jal, addi, lui, lb	2018-10-26 22:52:39 +02:00
Olof Kindgren	e10c41be8d	Initial commit	2018-10-23 23:45:41 +02:00