Currently there are no testbenches provided with the project but the CI will still verify that each push and pull request to the project can be compiled. If/when tests are added they will also be executed with each push and PR.
VUnit performs dependency scanning to determine compile order. If an early compiled file has an used reference to a library for which no files have been compiled yet, that library is not recognized and leads to a compile error.
Such unused library reference have been removed.
These mocks allow for a pure VHDL CI environment. The mocks are currently empty and provide no functionality. This is acceptable as long as no testbenches depend on them.
For now their primary purpose is to allow the project to be compiled by GHDL.
Some files also reference the UNISIM library. These references are not used and have been removed.
The attribute is defined as
attribute recursive_synthesis: boolean
but is frequently used with the integer value 1, for example
attribute recursive_synthesis of gate : function is 1;
These ones have been changed to true
This is a basic core description file. It allows other FuseSoC
projects to depend on the a2i core and it defines a synth target
that can be used to run synthesis against different Xilinx devices.
If a2i is available to FuseSoC, the synthesis target can be run with
fusesoc run --target=synth a2i
In order to run synthesis against a specific device, add --part=<part>
as a core option, e.g.
fusesoc run --target=synth a2i --part=xc7a200tsbg484-1
This adds a requirement that all contributed patches have the
Developer Certificate of Origin (ie a Signed-off-by)
Signed-off-by: Michael Neuling <mikey@neuling.org>
