wfjm
dfa2a91a18
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
Walter F.J. Mueller
a2264ab463
23 line interrupt mapper for full system configuration
2017-01-29 14:08:04 +01:00
Walter F.J. Mueller
2b5cfb7d96
- Code base cleaned-up for vivado, fsm now inferred
...
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
2016-06-26 16:02:42 +00:00
Walter F.J. Mueller
4a032e9436
- added RH70/RP/RM big disk support
...
- many cleanups
2015-05-14 17:00:36 +00:00
Walter F.J. Mueller
e91847f8db
- added support for Vivado
...
- added support for Nexys4 and Basys3 boards
- added RL11 disk support
- lots of documentation updated
2015-03-09 19:26:25 +00:00
Walter F.J. Mueller
3f455d5236
- interim release w11a_V0.532 (untagged)
...
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
2011-11-20 12:31:43 +00:00
Walter F.J. Mueller
c3d40ba4b9
- interim release w11a_V0.52 (untagged)
...
- migrate to rbus protocol verion 3
- reorganize rbus and rlink modules, many renames
2011-01-02 13:39:34 +00:00
Walter F.J. Mueller
16ce5b2091
- interim release w11a_V0.51 (untagged)
...
- migrate to ibus protocol verion 2
- nexys2 systems now with DCM derived system clock supported
- sys_w11a_n2 now runs with 58 MHz clksys
2010-11-27 23:17:50 +00:00
Walter F.J. Mueller
3335c61549
initial source upload (no docs yet)
2010-07-09 18:14:38 +00:00
