- sys_tst_sram_arty: add system and tb
- sramif_mig_arty: add SRAM to DDR via MIG adapter for arty
- cdc_pulse: add clock domain crossing for a slowly changing value
- cdc_vector_s0: add ENA port (now used in cdc_pulse)
- tst_mig/util.tcl: test_rwait: add optional lena argument
- viv_tools_build.tcl: downgrade SSN critical warnings to warnings
- Vivado is used with -fsm_extraction one_hot. Starting with Vivado 2016.3
this triggers fsm recognition and re-coding of two gray counter modules.
This not only defeats the purpose of the gray coded counter, it also
caused some constraints to fail. Added attributes to prevent fsm extraction
- the logic of `connect_hw_server` and `get_hw_servers` changed after Vivado
2015.1. The `make <design>.vconfig` command worked up to Vivado 2016.2 due
to some recovery mechanism, and finally broke with 2016.3. Fixed the
call to `get_hw_servers`.
