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11 Commits

Author SHA1 Message Date
wfjm
74ad445c1e Some minor updates: 
- tbrun: add --list option
- ti_w11: add add -ar,-n4d (ddr versions)
- travis: run all  sys_tst_sram,sys_w11a also for arty (cover ddr)
- tst_mig/test_mem.tcl: add low level iface tests
- comment changes
 2019-01-13 09:46:54 +01:00
wfjm
cb7b906089 Add memory tester for Arty and MIG 
- sys_tst_sram_arty: add system and tb
- sramif_mig_arty: add SRAM to DDR via MIG adapter for arty
- cdc_pulse: add clock domain crossing for a slowly changing value
- cdc_vector_s0: add ENA port (now used in cdc_pulse)
- tst_mig/util.tcl: test_rwait: add optional lena argument
- viv_tools_build.tcl: downgrade SSN critical warnings to warnings
 2019-01-03 09:15:07 +01:00
wfjm
f50a85e646 add sys_tst_mig_arty system: a MIG tester 2019-01-01 22:41:44 +01:00
wfjm
14362b2a56 Add basic DDR memory support 
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
 2018-12-31 10:00:14 +01:00
wfjm
22bb8e011c reorganize dcm/mmcm/ppl sim models 
- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
 2018-11-09 17:48:56 +01:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
Walter F.J. Mueller
92e149437d Fix license disclaimer 2016-12-26 21:27:33 +01:00
Walter F.J. Mueller
238b6e4276 rename .cvsignore -> .gitignore 2016-12-17 16:28:37 +01:00
Walter F.J. Mueller
5983b0bb2a - upgraded CRAM controller, now with 'page mode' support 
- new test bench driver tbrun, give automatized test bench execution
 2016-10-15 07:42:21 +00:00
Walter F.J. Mueller
2b5cfb7d96 - Code base cleaned-up for vivado, fsm now inferred 
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
 2016-06-26 16:02:42 +00:00
Walter F.J. Mueller
e1479d4e5d - Add Arty support (BRAM only) 
- Add sysmon/xadc support (for nexys4,basys3,arty designs)
- Add Vivado simulator support (DPI not yet working)
 2016-03-19 15:45:59 +00:00