5 Commits

Author	SHA1	Message	Date
Walter F.J. Mueller	5983b0bb2a	- upgraded CRAM controller, now with 'page mode' support ... - new test bench driver tbrun, give automatized test bench execution	2016-10-15 07:42:21 +00:00
Walter F.J. Mueller	2b5cfb7d96	- Code base cleaned-up for vivado, fsm now inferred ... - xsim support complete (but many issues to be resolved yet) - Added configurable w11a cache - Removed some never documented and now strategically obsolete designs	2016-06-26 16:02:42 +00:00
Walter F.J. Mueller	e1479d4e5d	- Add Arty support (BRAM only) ... - Add sysmon/xadc support (for nexys4,basys3,arty designs) - Add Vivado simulator support (DPI not yet working)	2016-03-19 15:45:59 +00:00
Walter F.J. Mueller	e91847f8db	- added support for Vivado ... - added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated	2015-03-09 19:26:25 +00:00
Walter F.J. Mueller	d87ac86f53	- migrate to rlink protocol version 4 ... - Goals for rlink v4 - 16 bit addresses (instead of 8 bit) - more robust encoding, support for error recovery at transport level - add features to reduce round trips - improved attention handling - new 'list abort' command - For further details see README_Rlink_V4.txt - use own C++ based tcl shell tclshcpp instead of tclsh	2014-12-20 16:39:52 +00:00