7 Commits

Author	SHA1	Message	Date
wfjm	0c395856d7	add memlib/fifo_simple_dram + test benches ... - add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period	2019-02-22 19:09:42 +01:00
wfjm	dfa2a91a18	get disclaimers in line with GPL V3 License.txt	2018-01-02 21:57:40 +01:00
Walter F.J. Mueller	2b5cfb7d96	- Code base cleaned-up for vivado, fsm now inferred ... - xsim support complete (but many issues to be resolved yet) - Added configurable w11a cache - Removed some never documented and now strategically obsolete designs	2016-06-26 16:02:42 +00:00
Walter F.J. Mueller	e91847f8db	- added support for Vivado ... - added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated	2015-03-09 19:26:25 +00:00
Walter F.J. Mueller	3f455d5236	- interim release w11a_V0.532 (untagged) ... - re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std	2011-11-20 12:31:43 +00:00
Walter F.J. Mueller	e15295649e	- interim release w11a_V0.531 (untagged) ... - many small changes to prepare upcoming support for Spartan-6 and usage of Cypress FX2 USB interface on nexys2/3 and atlys boards	2011-09-12 20:52:31 +00:00
Walter F.J. Mueller	3335c61549	initial source upload (no docs yet)	2010-07-09 18:14:38 +00:00