Emil J. Tywoniak
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9717a558cc
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intel: register bram celltypes
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2026-05-22 18:39:42 +02:00 |
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Emil J. Tywoniak
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d7b6f1c095
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rtlil_bufnorm: ignore timing info harder
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2026-05-22 18:39:42 +02:00 |
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Emil J. Tywoniak
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14eaedace4
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gowin: replace positional arguments in cells_sim.v with named
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2026-05-22 18:39:42 +02:00 |
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Emil J. Tywoniak
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a93faf811a
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Revert "techmap: call hierarchy on map files to determine port directions"
This reverts commit eabbf6d225.
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2026-05-22 18:39:42 +02:00 |
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Emil J. Tywoniak
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81b99d83f5
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hierarchy: tolerance for apparent recursive instances in techmap files
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2026-05-22 18:39:42 +02:00 |
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Emil J. Tywoniak
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0eb215dd97
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techmap: call hierarchy on map files to determine port directions
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2026-05-22 18:39:42 +02:00 |
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Emil J. Tywoniak
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b7c9c8eea6
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tests: use memory -bram-register in tests/bram
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2026-05-22 18:39:41 +02:00 |
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Emil J. Tywoniak
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67de0c8c9e
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memory: add -bram-register
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2026-05-22 18:39:05 +02:00 |
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Emil J. Tywoniak
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88aa5f190b
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memory_bram: add -register
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2026-05-22 18:39:05 +02:00 |
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Emil J. Tywoniak
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5e313a19a0
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ffmerge: initvals signorm compatibility fixup
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2026-05-22 18:39:05 +02:00 |
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Emil J. Tywoniak
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eb6dd47bd6
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timinginfo: special-case $specify2 in signorm invariant
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2026-05-22 18:39:04 +02:00 |
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Emil J. Tywoniak
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5bfb631085
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opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
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2026-05-22 18:38:37 +02:00 |
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Emil J. Tywoniak
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bd8738de15
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connect: remove input ports on conflict
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2026-05-22 18:38:37 +02:00 |
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Emil J. Tywoniak
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aecc173f83
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opt_dff: sigma harder, FfDataSigMapped
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2026-05-22 18:38:37 +02:00 |
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Emil J. Tywoniak
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7382be6962
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ff: add FfDataSigMapped
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2026-05-22 18:38:37 +02:00 |
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Emil J. Tywoniak
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be7beaf91a
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opt_dff: temporarily disable signorm due to muxtree traversal
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2026-05-22 18:38:37 +02:00 |
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Emil J. Tywoniak
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95eae1aa6d
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tests: fix rtlil roundtrip test
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2026-05-22 18:38:36 +02:00 |
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Emil J. Tywoniak
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21bed1a411
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design: fix signorm commit connectivity to design
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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6c2a90affc
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cxxrtl: ignore $input_port
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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faa1a1065c
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flatten: redo signormalization to work around fanout issue
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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bd437f207f
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abstract: fix test signorm
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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4f665d6efc
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signorm: disable passes that use rewrite_sigspecs
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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6447a39c0c
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aiger: ignore $input_port
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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8267dee75a
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check: stitch info about $connect ports together for driver analysis
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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b42136aa8c
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signorm: remove $input cells when leaving
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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5c5df513d1
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abstract: skip $input_port cells
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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dad6277a25
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flatten: skip $input_port cells in template module
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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d541def612
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signorm: skip const when fixing fanout
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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68bb5c6b94
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signorm: disable in passes that use swap_names
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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4d2a6f2b7a
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opt_expr: fix invert_map
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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422a505435
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satgen: support $connect
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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fb03a34277
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rtlil: add dump_sigmap for hacky signorm debugging
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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b859080ef2
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techmap: disable signorm more
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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6575e7f1df
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techmap: disable signorm
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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2f7d0913fc
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opt_hier: disable signorm
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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6b06869242
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timinginfo: disable output wire check due to signorm
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2026-05-22 18:37:56 +02:00 |
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Emil J. Tywoniak
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6d08c53429
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rtlil: forbid rewrite_sigspecs in signorm
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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bb2d6f0e2a
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opt_merge_inc: re add initvals deletion
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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07628a4042
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synth_ice40: always read abc9 model to understand port direction
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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5b6b11dd44
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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80a440ed2d
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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69c9f3e619
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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9d86a6636c
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wreduce: fixup initvals after setPort
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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e5266d0fbc
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ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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3dc45005f2
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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af48c1cdfb
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rtlil: fix zero width SigSpec crash in signorm setPort unsetPort
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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80ca3174ea
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bug2920: disable
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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e6515cfd93
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rtlil_bufnorm: fix cell deletion deferral bug
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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28013eccbc
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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dcc4cbea2f
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check: don't fail on $input_port
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2026-05-22 18:37:13 +02:00 |
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