27 Commits

Author	SHA1	Message	Date
aap	e000f5b5a7	added rim10 format loader	2020-09-03 14:38:22 +02:00
aap	716317c8ce	lots of additions and changes	2019-12-05 00:31:20 +01:00
aap	9d08e7306e	KA compatibility	2019-11-04 09:33:03 +01:00
aap	77c02726f5	verilog: passing diags part5	2019-10-29 18:17:32 +01:00
aap	a8b07f4340	verilog: passing diag part 3	2019-10-29 14:13:52 +01:00
aap	b96e2d468d	verilog: passing diags part2	2019-10-28 22:57:28 +01:00
aap	8975e4beb4	verilog: passing diags part1	2019-10-28 21:43:14 +01:00
aap	2bf63ab065	fixes	2019-10-27 17:12:55 +01:00
aap	b82dc449b8	fixed emu; new verilog code; fe6 for fpga	2019-10-26 16:49:04 +02:00
aap	28cc63f3ba	added network memory; some work on cmdline interface	2018-08-15 14:18:52 +02:00
aap	ae8c95d8e3	small change	2017-01-15 20:23:19 +01:00
aap	c74dad4bee	implemented floating point	2016-12-11 17:23:06 +01:00
aap	d8edd19b0d	implemented mul and div subroutines	2016-12-10 19:18:16 +01:00
aap	534d4521c3	added quartus project files	2016-12-10 00:00:16 +01:00
aap	69613da23e	changed verilog code for synthesis	2016-12-09 23:31:27 +01:00
aap	45bd177a73	verilog character instructions	2016-11-24 16:13:49 +01:00
aap	844810b249	verilog BLT	2016-11-24 11:04:41 +01:00
aap	f926fd9098	BLK	2016-11-23 09:52:46 +01:00
aap	db93c803c8	work on IOT, AR, SH and SC	2016-11-21 11:39:40 +01:00
aap	2268d61557	work on AR and MQ	2016-11-17 21:40:20 +01:00
aap	a1d5d59e04	some more AR stuff	2016-11-17 00:54:09 +01:00
aap	9c3ca3988f	basic E cycle working, S done	2016-11-16 17:06:27 +01:00
aap	712c0bddf6	implemented S cycle, started E	2016-11-15 23:57:55 +01:00
aap	dff2d4cff2	verilog instruction decoding	2016-11-14 23:44:16 +01:00
aap	a2f609fe66	implemented I and A cycles in verilog	2016-11-14 07:01:05 +01:00
aap	14a82a7e61	rewrote the verilog code	2016-11-13 02:06:34 +01:00
aap	fb47930b1b	started to write a verilog simulation	2016-11-09 19:24:07 +01:00