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Rob Landley 11c1ba7c5a Separate out predecoder. (Mostly Jeff's work.)
2019-11-15 02:21:29 -06:00
synth
Add reset generator to work around Lattice ignoring reset values. Fixes ROM decoder, reduce logic size by 8.5%
2019-04-02 17:52:39 -04:00
testrom
some more instruction colation
2019-09-26 21:15:44 -04:00
asymmetric_ram.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
bus_monitor.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
clk_sim.vhd
Actually add sim model for Lattice HF clk
2019-03-08 01:10:20 -05:00
components_pkg.vhd
Shuffle types around more logically, add comments, split pkg/body builds.
2019-11-15 01:41:16 -06:00
conv.c
Change back to complete ROM tests. NOTE: may overflow FPGA
2019-09-22 23:06:25 -04:00
cpu2j0_pkg.vhd
Shuffle types around more logically, add comments, split pkg/body builds.
2019-11-15 01:41:16 -06:00
cpu_bulk_sram.vhd
With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.
2019-03-25 21:50:49 -04:00
cpu_lattice.vhd
Clean up data and instruction bus, and decoders. Hand hacked, should be auto gen
2019-04-02 22:23:49 -04:00
cpu_pure_tb.vhh
With single port RAM
2019-03-03 23:16:35 -05:00
cpu_simple_sram.vhd
Change back to complete ROM tests. NOTE: may overflow FPGA
2019-09-22 23:06:25 -04:00
cpu_sram.vhd
Add testrom, modified for small memory... enable tests if you need in Makefile
2019-03-03 20:55:24 -05:00
cpu_up5k_42s.vhd
Clean up data and instruction bus, and decoders. Hand hacked, should be auto gen
2019-04-02 22:23:49 -04:00
cpu.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
data_bus_pkg.vhd
Clean up data and instruction bus, and decoders. Hand hacked, should be auto gen
2019-04-02 22:23:49 -04:00
datapath_pkg.vhd
Shuffle types around more logically, add comments, split pkg/body builds.
2019-11-15 01:41:16 -06:00
datapath.vhd
Shuffle types around more logically, add comments, split pkg/body builds.
2019-11-15 01:41:16 -06:00
decode_core.vhd
Separate out predecoder. (Mostly Jeff's work.)
2019-11-15 02:21:29 -06:00
decode_pkg.vhd
Separate out predecoder. (Mostly Jeff's work.)
2019-11-15 02:21:29 -06:00
decode_table_reverse.vhd
Shuffle types around more logically, add comments, split pkg/body builds.
2019-11-15 01:41:16 -06:00
decode_table_rom.vhd
Shuffle types around more logically, add comments, split pkg/body builds.
2019-11-15 01:41:16 -06:00
decode_table_simple.vhd
Shuffle types around more logically, add comments, split pkg/body builds.
2019-11-15 01:41:16 -06:00
decode_table.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
decode.vhd
Sync RAM register file implemntation
2019-03-13 17:05:56 -04:00
free42.pcf
Minor change to pinouts for v1.1 board
2019-03-26 12:05:44 -04:00
ghdl_lattice.sh
Separate out predecoder. (Mostly Jeff's work.)
2019-11-15 02:21:29 -06:00
ghdl_up5k.sh
Add reset generator to work around Lattice ignoring reset values. Fixes ROM decoder, reduce logic size by 8.5%
2019-04-02 17:52:39 -04:00
ghdl.sh
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
lattice_ebr.vhd
A few warnings fixed
2019-03-13 19:40:04 -04:00
lattice_spr_wrap.vhd
With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.
2019-03-25 21:50:49 -04:00
lattice_spr.vhd
With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.
2019-03-25 21:50:49 -04:00
lattice_tb.vhd
Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk
2019-03-08 01:09:52 -05:00
monitor_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
mult_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
mult.vhd
Rename things to avoid "hides" warnings.
2019-11-12 06:16:14 -06:00
nvc_lattice.sh
Add sim by default and wave viewer ctl file for reg file debug
2019-03-08 01:37:20 -05:00
nvc_simple.sh
With single port RAM
2019-03-03 23:16:35 -05:00
nvc.sh
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
predecode_pkg.vhd
Separate out predecoder. (Mostly Jeff's work.)
2019-11-15 02:21:29 -06:00
ram_init.vhd
some more instruction colation
2019-09-26 21:15:44 -04:00
ram.img
some more instruction colation
2019-09-26 21:15:44 -04:00
ram.sh
First synthesys for ICE40 UP5k with everything to blink LEDs
2019-03-04 01:17:33 -05:00
README
Add a README.
2019-11-11 05:25:45 -06:00
reg.gtkw
Attempt to avoid write conflict on Lattice EB RAM
2019-03-15 16:46:15 -04:00
register_file_sync.vhd
Attempt to avoid write conflict on Lattice EB RAM
2019-03-15 16:46:15 -04:00
register_file.vhd
Sync RAM register file implemntation
2019-03-13 17:05:56 -04:00
simple_ram.vhd
some more instruction colation
2019-09-26 21:15:44 -04:00
timeout_cnt.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
up5k_tb.vhd
Minor change to pinouts for v1.1 board
2019-03-26 12:05:44 -04:00
upduino2.pcf
Continue simple cleanups of pinouts and platform split. Still doesn't work, though
2019-03-27 21:04:53 -04:00
verific
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00

README 

# J-core j1 for Lattice ice40 FPGA, with GHDL build/test script

This is a stripped-down build of https://j-core.org j2 processor which
is instruction set compatibile with the full j2 but has no I/O devices,
DRAM controller or SMP support.

Install https://github.com/ghdl/ghdl and run ./ghdl_lattice.sh to build and
simulate this CPU running a test rom. (If it prints the C0 line all instruction
tests passed.) See the testrom/ directory for ROM source, for bare metal
elf toolchain build instructions see:
  http://lists.j-core.org/pipermail/j-core/2019-October/000867.html

A working ICE40 UltraPlus5k bitstream was produced from this source via
Lattice's Synplify+IceCube2 toolchain. It's also been tested with GHDL, NVC,
Xilinx WebPack ISE, and Vivado.

We are working to get a fully open source VHDL toolchain (built from
ghdl+ghdlsynth+yosys+abc) creating bitstreams from that (it doesn't yet).
For build instructions for that see:
  http://lists.j-core.org/pipermail/j-core/2019-November/000868.html
Description
J-core SOC for ice40 FPGA
Readme 379 KiB
Languages
VHDL 75.2%
Assembly 14.1%
C 9.3%
Shell 0.8%
Linker Script 0.3%
Other 0.3%