1
0
mirror of https://github.com/livingcomputermuseum/UniBone.git synced 2026-01-28 04:47:46 +00:00
Commit Graph

71 Commits

Author SHA1 Message Date
Joerg Hoppe
cc42d60409 type in dir name 2019-09-02 15:37:29 +02:00
Joerg Hoppe
15d22c8e25 /home/joerg/retrocmp/dec/UniBone/workspace 2019-09-01 06:47:30 +02:00
Joerg Hoppe
f13b35bc08 KW11 LKS line monitor bit can only be cleared 2019-08-31 17:29:48 +02:00
Joerg Hoppe
30df58f42c fix baudrate bit width 2019-08-30 13:38:34 +02:00
Joerg Hoppe
e3ca35f24b device parameter interurpt vector&level not udpated 2019-08-28 16:45:52 +02:00
Joerg Hoppe
52d646973d delay after powercycle, so system is stable for next operation 2019-08-28 16:45:08 +02:00
Joerg Hoppe
d058310e53 CPU20 power start/power fail 2019-08-27 19:05:41 +02:00
Joerg Hoppe
6f2adbd216 levelchange(PSW) on RTI 2019-08-27 13:31:37 +02:00
Joerg Hoppe
827515eb8c module rename for upcoming intr_slave 2019-08-26 13:51:34 +02:00
Joerg Hoppe
ea91180f28 Connected CPU20 to INTR,INIT,Power ON/OFF.
PRU INTR routing still do to.
2019-08-25 09:17:28 +02:00
Joerg Hoppe
f938c8ba8a Power OFF event now from ACLO
PRU bugfix: if DMA cycle started by register access cycle
Extended interface for emulated CPU
2019-08-22 17:30:21 +02:00
Joerg Hoppe
fa454f646c added listing for easy loading 2019-08-19 13:26:22 +02:00
Joerg Hoppe
3d1d9d3cf6 ACLO/DCLO/INIT moved from PRU to ARM
INTR/DMA request params linked to device params on change
2019-08-19 13:12:42 +02:00
Joerg Hoppe
e2229871de PDP-11 test program for concurrent INTR/DMA
Serial, Clock, RL02, RK05, MSCP
2019-08-19 12:57:18 +02:00
Joerg Hoppe
8ff33a0be1 Infrastructure for emulated CPUs: Bus arbitrator, Interrupt fielding processor 2019-08-16 19:04:12 +02:00
Jörg Hoppe
155b02a089 Merge pull request #3 from livingcomputermuseum/master
Fixes for MSCP with new DMA/IRQ infrastructure
2019-08-16 14:25:44 +02:00
Josh Dersch
6f1b476716 Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait).
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes
with latest PRU code -- MSCP works reliably on PDP-11/84 again.
2019-08-16 02:23:32 +02:00
Josh Dersch
073a2334b6 Fixes for MSCP after Joerg's INTR/DMA rewrites:
- Fixed programmable interrupt vector (was broken after changes)
- Fixed interrupts during MSCP 4-stage init to atomically update SA register; 4.3bsd now boots.
2019-08-14 09:46:32 +02:00
Josh Dersch
1d4fe694ae Merge remote-tracking branch 'upstream/master' 2019-08-12 17:28:19 -07:00
Joerg Hoppe
7eaa7c0729 RL11 changed to atomically INTR/CSR write. Passes exerciser ZRLKB3 now for 2h. 2019-08-12 12:21:56 +02:00
Joerg Hoppe
5ba6142b52 cleanup 2019-08-10 12:10:44 +02:00
Joerg Hoppe
39caffd6e6 Emulated DL11: stream interface parallel to RS232.
demo: "dl11 rcv" and "dl11 wait" script extension
cleanup
2019-08-10 10:19:05 +02:00
Joerg Hoppe
313957631f Cleanup, fixes Interrupt logic, RL11 tests 2019-08-08 07:32:08 +02:00
Joerg Hoppe
855f1a6cee GitHub usability 2019-08-05 09:28:07 +02:00
Joerg Hoppe
d9b49ac70f Fix GitHub repository 2019-08-05 08:37:03 +02:00
Joerg Hoppe
10cf1598f1 Big summer rework:
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
2019-08-02 20:10:48 +02:00
Joerg Hoppe
974aeed8eb Big summer rework:
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
2019-08-02 16:45:54 +02:00
Joerg Hoppe
471df2d8ea PRU1: multiple parallel timeouts 2019-07-03 21:48:49 +02:00
Joerg Hoppe
3f783e5000 Missing source added 2019-07-02 13:02:06 +02:00
Joerg Hoppe
04869fb46f PRU statemachines easier to control from main thread 2019-07-02 07:09:01 +02:00
Joerg Hoppe
e23b2cf4d3 Dl11w rcv intr 2019-06-26 07:48:31 +02:00
Joerg Hoppe
01efdee04a DL11W interrupt tests&fixes 2019-06-25 16:47:17 +02:00
Joerg Hoppe
81c3295e31 DL11 cleanup&fixes 2019-06-24 17:25:20 +02:00
Joerg Hoppe
28ab69050c break enable, maintenance loopback 2019-06-24 14:51:18 +02:00
Joerg Hoppe
b749ce5897 SLU compiles, minimal function 2019-06-24 12:03:47 +02:00
Joerg Hoppe
4062386b97 Multiple parallel instances of device::worker() possible 2019-06-23 12:00:13 +02:00
Joerg Hoppe
3952cb93b0 Enable devices individually over param "enabled"
UNIBUS addr, intr vector, level setable
2019-06-20 21:58:04 +02:00
Josh Dersch
00627567bf Removing merge marker from menu_devices.cpp. 2019-06-19 22:48:32 +02:00
Josh Dersch
76166ce7a1 Merge remote-tracking branch 'upstream/master' 2019-06-19 22:26:49 +02:00
Joerg Hoppe
ccd6747892 Cleanup, EOL Windows->Unix 2019-06-19 07:30:26 +02:00
Joerg Hoppe
7866641a3d added zkma memtest 2019-06-18 21:06:02 +02:00
Joerg Hoppe
eaa0e0dbe0 Merge branch 'master' of https://github.com/j-hoppe/UniBone 2019-06-18 21:04:04 +02:00
Joerg Hoppe
264f6e5085 Cleanup incomplete commits 2019-06-18 21:03:02 +02:00
Josh Dersch
8f72cb2324 Merge remote-tracking branch 'upstream/master'
Conflicts:
	10.03_app_demo/2_src/menu_devices.cpp
2019-06-18 20:54:06 +02:00
Josh Dersch
7626b50c52 Merge remote-tracking branch 'upstream/master'
Conflicts:
	10.01_base/2_src/arm/storagedrive.cpp
	10.01_base/2_src/arm/unibusadapter.cpp
	10.01_base/2_src/arm/unibusadapter.hpp
	10.01_base/2_src/pru1/pru1_statemachine_dma.c
	10.02_devices/2_src/mscp_server.cpp
	10.02_devices/2_src/mscp_server.hpp
	10.02_devices/2_src/rk05.hpp
	10.02_devices/2_src/rk11.cpp
	10.02_devices/2_src/rk11.hpp
	10.02_devices/2_src/rl11.cpp
	10.02_devices/2_src/uda.cpp
	10.03_app_demo/2_src/makefile
	10.03_app_demo/2_src/menu_devices.cpp
2019-06-18 20:50:33 +02:00
Joerg Hoppe
1a79abb89f Cleanup incomplete commits 2019-06-18 20:38:07 +02:00
Joerg Hoppe
a4dc6af85c New ".input" command for "demo" scripts 2019-06-14 16:33:48 +02:00
Joerg Hoppe
db0167afe1 Version 2019-06: many changes
PRU1 code split into multiple images
1. test functions
2. UNIBUS operation

PRU1 bus latch interface
Write byte/bits access not with MACROS (random optimizer influence),
now with *_helper() procedures. Same timing, more determinism, much code saving.
Nono more  ASM code to write PRU0 XFER area.

demo: menu to test UNIBUS signals directly

rework "Arbitration" logic: now 3-fold
Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER
- no Arbitrator (SACK penidng for 11/34 Konsole) (NONE)
- phyiscal PDP_11 CPU is Arbitrator (CLIENT)
- UniBone implements Arbitrator (MASTER)
- Same PRU code loop handles all arbitration types

PRU buslatch timing slower, for some problematic PCBs

 More aggressive bus latch  selftest
 (mixed patterns, running on PRU now)

Refinement of ready-to-run scripts
- Adapted to changed "demo" menu
- new name scheme
<OS>_<boot- drive>_<PDP-11CPU>
indicates
- which OS is run
- which disk emulation is used and what is the boot device
- what is the (minimum) PDP-11 to run that

Merged in Joshs DMA timing for 11/84
UNIBUS master cycles waits 350 us before MSYN, instead 150.

Merged in Joshs DMA request queue
multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially

Merged in Joshs MSCP driver
- Build RT-11v5.5 for MSCP
- added boot loader "du.lst"

MSCP run scrips
2.11BSD on MSCP on PDP-11/44
RT11 on MSCP

Fix: image file sizing
Disk image file exptend automatically if block beyond current file end is written
2019-06-14 16:31:01 +02:00
Josh Dersch
a0bdd14810 Fix for VMS bootstrap (sanity check was violated, we now log the case rather than aborting).
Fixed interrupt behavior (docs around the IE flag at init are vague -- looks like IE controls interrupts only
during the initialization; afterwards interrupts are always enabled regardless.)

V8 Research Unix now boots (tested on VAX-11/750).
2019-05-22 10:16:57 +02:00
Josh Dersch
1ad88b6778 Adding copyright info to file headers. 2019-05-18 02:16:05 +02:00