24 Commits

Author	SHA1	Message	Date
Andrew Kay	aeb39bfb69	Added part numbers	2020-02-28 10:46:48 -06:00
Andrew Kay	0a92b621e8	Prototype PCB	2020-02-27 22:51:38 -06:00
Andrew Kay	891390cb84	Attempt DP8340 and DP8341 shims	2020-02-21 20:43:52 -06:00
Andrew Kay	49abcf7e2b	Add data, data_available and data_read	2020-02-18 07:55:13 -06:00
Andrew Kay	811a048685	Initial attempt at receiver	2020-02-17 20:47:46 -06:00
Andrew Kay	2b81a4a961	Clean up bit timer	2020-02-15 09:41:37 -06:00
Andrew Kay	81c6172e7b	Bit timer module	2020-02-14 20:13:01 -06:00
Andrew Kay	a95e83bd5e	Clean up full and data loading	2020-02-14 07:58:14 -06:00
Andrew Kay	a8f0949842	Parameterize tx_delay_buffer size	2020-02-14 06:57:50 -06:00
Andrew Kay	a7ee9c502d	Add tx_delay size comment	2020-02-13 19:26:17 -06:00
Andrew Kay	d4eaeecec2	Hello world	2020-02-12 23:13:21 -06:00
Andrew Kay	c859688931	Initial attempts at multiple word transmission	2020-02-12 19:44:43 -06:00
Andrew Kay	cc7023d35f	Cleanup	2020-02-11 07:51:10 -06:00
Andrew Kay	13eb0f52bd	Adding tx_inverted and updating pins	2020-02-10 22:26:39 -06:00
Andrew Kay	ff200bf26f	Adding tx_delay	2020-02-10 22:13:55 -06:00
Andrew Kay	7bf43eede5	Remove BIT_ALIGN state and improve active	2020-02-10 21:56:35 -06:00
Andrew Kay	05663ab5b7	End sequence	2020-02-09 14:53:23 -06:00
Andrew Kay	7a78447c6c	Cleanup clocks	2020-02-09 09:50:40 -06:00
Andrew Kay	42a46806c8	Parity bit	2020-02-09 09:35:00 -06:00
Andrew Kay	77821b3f11	Data	2020-02-08 20:03:13 -06:00
Andrew Kay	b9ed29bd4b	Code violation and sync bit	2020-02-08 19:03:36 -06:00
Andrew Kay	9faae78fd8	Quiesce pattern	2020-02-08 18:55:11 -06:00
Andrew Kay	0b618d6b35	Adding a 19 MHz clock	2020-02-08 17:43:09 -06:00
Andrew Kay	ad7ba12d2c	Verilog templating	2020-02-04 22:11:14 -06:00