Gyorgy Szombathelyi
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42a828913f
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Archie: register some SDRAM signals for better timing properties
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2019-11-02 18:59:56 +01:00 |
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Gyorgy Szombathelyi
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b5883c7c2c
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[Archie] Risc Developments IDE interface
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2019-11-02 18:59:34 +01:00 |
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Gyorgy Szombathelyi
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07de4fb657
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Archie: eliminiate a < comparision in the SDRAM controller
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2019-10-26 18:58:25 +02:00 |
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Gyorgy Szombathelyi
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1dbc66ab68
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Archie: use a bit less cycles in the SDRAM controller
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2019-10-23 14:56:12 +02:00 |
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Gyorgy Szombathelyi
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f296e03f53
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Archie: clean up SDRAM controller
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2019-10-23 12:45:40 +02:00 |
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Gyorgy Szombathelyi
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db288bcdae
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Archie: don't consume new pixel data during hsync
Fixes BIA bounce demo
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2019-10-22 19:57:08 +02:00 |
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Gyorgy Szombathelyi
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cb13fcef8d
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Archie: use 2 deterministic places for requesting new data in VIDC
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2019-10-22 19:57:08 +02:00 |
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Gyorgy Szombathelyi
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ef4be11a52
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Archie: vidc flybk should be active after the end of the display
...until the first displayed one, according to the datasheet.
Fixes Elite in 15kHz
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2019-10-22 19:57:08 +02:00 |
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Gyorgy Szombathelyi
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434ea845de
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Archie: transfer hsync to cpuclk domain for using in MEMC
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2019-10-21 19:52:32 +02:00 |
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Gyorgy Szombathelyi
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40e8f7e844
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Archie: re-use the already fetched burst
As a primitive 128 bit cache
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2019-10-21 17:37:06 +02:00 |
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Gyorgy Szombathelyi
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1b4884aaa6
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Archie: fix possible bug when wb_we change too soon after wb_ack
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2019-10-21 12:09:42 +02:00 |
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Gyorgy Szombathelyi
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1a4cdecac7
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Archie: 128 bit burst read for VIDC
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2019-10-20 20:30:34 +02:00 |
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Gyorgy Szombathelyi
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54d155bcf0
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Archie: use built-in SDRAM burst feature
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2019-10-20 13:35:53 +02:00 |
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Gyorgy Szombathelyi
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966e01d66c
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Revert "Archie: 128bit SDRAM interface (by Sorgelig)"
This reverts commit 375c423a85.
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2019-10-19 23:30:50 +02:00 |
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Gyorgy Szombathelyi
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39fafc65b8
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Archie: replace vidc fifo with DCFIFO component to fix clock domain crossing issues
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2019-10-19 17:17:17 +02:00 |
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Gyorgy Szombathelyi
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4a1a470d0e
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Archie: change video timing events to simple equality checks
Display event registers less likely to glitch
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2019-10-18 21:57:11 +02:00 |
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Gyorgy Szombathelyi
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375c423a85
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Archie: 128bit SDRAM interface (by Sorgelig)
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2019-10-18 20:56:39 +02:00 |
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Gyorgy Szombathelyi
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7122e993fc
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Archie: reduce clock to 40MHz
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2019-10-18 20:39:40 +02:00 |
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Gyorgy Szombathelyi
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46bd0dd0c1
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Archie: common FDC with the ST core
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2019-10-18 19:54:03 +02:00 |
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Gyorgy Szombathelyi
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9b19a1f1b8
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[Archie] Smart precharge for SDRAM
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2019-03-08 01:11:47 +01:00 |
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Gyorgy Szombathelyi
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5135fd9854
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[Archie] Spare some SDRAM cycles
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2019-03-07 22:37:52 +01:00 |
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Gyorgy Szombathelyi
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d774f5356b
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[Archie] Adjust SDRAM simulation
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2019-03-07 15:33:15 +01:00 |
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Gyorgy Szombathelyi
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dd445a01ca
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[Archie] Increase the CPU clock to 42MHz
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2019-03-05 23:04:43 +01:00 |
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Gyorgy Szombathelyi
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bb0141b3a8
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[Archie] Silence warnings
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2019-03-05 15:57:36 +01:00 |
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Gyorgy Szombathelyi
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0ee6b5b8df
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[Archie] VIDC: there's no horizontal cursor end register
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2019-03-05 13:40:48 +01:00 |
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Gyorgy Szombathelyi
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ca812da031
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[Archie] Remove obsolete files
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2019-03-03 15:24:20 +01:00 |
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Gyorgy Szombathelyi
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b6c3910709
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[Archie] FDC fixes
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2019-03-03 14:51:45 +01:00 |
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Gyorgy Szombathelyi
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1d60379857
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[Archie] Add CMOS RAM upload
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2019-03-02 22:47:58 +01:00 |
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Gyorgy Szombathelyi
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860a597248
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[Archie] Use standard IO for FDC with full read/write support
Needs firmware update
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2019-03-02 16:43:56 +01:00 |
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Gyorgy Szombathelyi
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99d8c93590
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[Archie] Synchronize reset signals in VIDC
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2019-02-24 03:13:15 +01:00 |
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Gyorgy Szombathelyi
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c8d2bb5c00
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[Archie] Use only one clock in the FDC
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2019-02-24 00:21:28 +01:00 |
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Gyorgy Szombathelyi
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da57e7d393
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[Archie] Improve SDRAM controller
Don't feed the SDRAM pins from combinatorial logic, that prevents
to use fast output registers.
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2019-02-14 20:55:53 +01:00 |
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Gyorgy Szombathelyi
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dd9e400334
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[Archie] Adjust SDRAM timings
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2019-02-09 01:21:38 +01:00 |
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Gyorgy Szombathelyi
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8d83a61d1d
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[Archie] Use only clk_32 in user_io and ioc
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2019-02-09 00:18:36 +01:00 |
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Gyorgy Szombathelyi
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7472f9339d
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[Archie] Use only one clock in vidc (port from MiSTer)
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2019-02-08 12:32:34 +01:00 |
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sleary78
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35cd4b2646
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removed the unused uart.
updated the boilerplates on a bunch of the .v files
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2016-05-23 20:23:21 +01:00 |
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sleary78
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6eb9b1c859
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adding the sdram model.
removed broken $display()
updated the SUPPORT environment variable
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2016-05-23 18:51:00 +01:00 |
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sleary78
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01bbfd2431
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Adding the achie source code.
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2016-05-23 17:05:43 +01:00 |
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