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Author SHA1 Message Date
Olof Kindgren
7d08abb92d Improve makehex.py 2022-03-09 21:00:06 +01:00
Olof Kindgren
2bb988b553 Add reset for mie_mtie 2022-02-09 18:15:08 +01:00
Olof Kindgren
b74344bb48 Store GDS file as artifact after OpenLANE build 2022-01-21 00:11:32 +01:00
somhi
09e49f784a added board_device_index : 2 to chameleon96 for programming 2022-01-13 23:11:12 +01:00
somhi
7624365325
chameleon96 board support added (#74) 
* chameleon96 board added
 2022-01-11 22:54:45 +01:00
Olof Kindgren
e59fe5346a Refactor docs and add interface documentation 2022-01-03 18:12:48 +01:00
Olof Kindgren
a121b19ec4 Document shift operations 2022-01-02 23:54:13 +01:00
Olof Kindgren
aa8550b937 Remove doc for removed modules 2022-01-02 22:10:33 +01:00
Olof Kindgren
d910becd7f Move dbus_dat/rs2/shamt storage to bufreg2 2022-01-02 22:10:33 +01:00
Olof Kindgren
f04a510393 Remove unused parameter from serv_mem_if 2022-01-01 22:50:28 +01:00
Olof Kindgren
0719381997 Add ViDBo support 2022-01-01 17:15:14 +01:00
Olof Kindgren
0ab7176d3b Fix testbench indentation 2022-01-01 17:15:14 +01:00
Olof Kindgren
7765567cf1 Add missing gate on mem_rd with CSR disabled 2021-12-29 00:17:00 +01:00
Olof Kindgren
28953fec4c Simplify shift_op signal 2021-10-08 22:42:02 +02:00
Olof Kindgren
9c4bdd4bfe Simplify branch_op/slt_op signals 2021-10-08 22:25:24 +02:00
Olof Kindgren
9d3ebf3e96 Replace mem_op with dedicated control signals 2021-10-05 12:52:29 +02:00
Olof Kindgren
e5c6e78820 Simplify MDU logic in serv_mem_if 2021-10-04 23:49:23 +02:00
Olof Kindgren
99f82af6eb Simplify optional MDU logic 2021-10-03 23:28:45 +02:00
Zeeshan Rafique
8843005407
updated vars declaration for modelsim (#63) 2021-10-03 23:15:54 +02:00
Olof Kindgren
48e250ea5e Clean up serv_state interface 2021-10-03 22:48:51 +02:00
Olof Kindgren
b929c31c29 Avoid printing directly in do_uart 2021-09-27 22:10:19 +02:00
Olof Kindgren
b15b5ed652 Add Github action to build with openlane+sky130 2021-08-30 22:13:42 +02:00
Klas Nordmark
52d0bf0938 Added openlane target and params.tcl with suitable openlane parameters for SERV 2021-08-30 22:13:42 +02:00
Olof Kindgren
2989051f44 Avoid enabling bufreg before instruction is decoded 2021-08-27 13:10:06 +02:00
Olof Kindgren
3971ca942e Fix up RVFI 2021-08-27 13:10:06 +02:00
Olof Kindgren
64f5ca0b7f Add missing reset on cnt_done 2021-08-27 13:10:06 +02:00
Olof Kindgren
781c07b7dc Properly reset stage_two_req signal 2021-08-27 13:10:06 +02:00
Olof Kindgren
b10a871499 Fix signedness bug on immediates 
The sign bit on immediates relied on the value of csr_imm_en from
the previous instruction. This fixes by gating with csr_imm_en
after it has been latched instead of before
 2021-08-27 13:10:06 +02:00
Olof Kindgren
d2a4243033 Add reset for new_irq register 2021-08-27 13:10:06 +02:00
Olof Kindgren
621baeff31 Always return 0 from reads to reg x0 in serv_rf_ram 2021-08-27 13:10:06 +02:00
Zeeshan Rafique
6e802cb9bc M-extension support for SERV 
* modified serv(ant) for MDU
* added dependency for mdu
* M-extension for SERV
* Updated README for running RV32IM compliance tests
* waive some lint warnings related to mdu
* added mdu param for arty_a7_35t
 2021-08-20 23:45:19 +02:00
Dhiru Kholia
dbe5236b4c Add support for EBAZ4205 'Development' Board 
References:

- https://github.com/fusesoc/blinky/pull/68/files (EBAZ4205 blinky)
- https://github.com/fusesoc/blinky#ebaz4205-development-board
- Existing 'arty_a7_35t' example

This PR also cleans up a bunch of whitespace issues (no functional
change).
 2021-08-15 19:46:37 +02:00
hakan-demirli
b845507e32 Update serv_timer.c 
Fix a typo 'fro'
 2021-08-10 09:38:21 +02:00
Olof Kindgren
8e073546b8 Prepare for release 1.1.0 2021-08-09 23:12:18 +02:00
Olof Kindgren
64ac4d6eb5 Fix badges 2021-08-09 16:35:31 +02:00
Olof Kindgren
eb50f8c83c Fix Github CI action 2021-08-09 16:14:52 +02:00
Olof Kindgren
d2467cf951 Update movie links 2021-08-09 15:22:58 +02:00
Olof Kindgren
18c8c65255 Fix RISC-V compliance instructions 2021-07-06 00:20:55 +02:00
Olof Kindgren
15246e3692 Fix Verilator waiver file 2021-07-05 23:59:19 +02:00
Dave Dribin
57af7204d1 Wire up servant.q output to both LED1 and UART TX 2021-06-28 09:10:04 +02:00
Dave Dribin
c561979c8e Minor update to .pcf 2021-06-28 09:10:04 +02:00
Dave Dribin
0375ba896f Move to board-specific top-level and file set 2021-06-28 09:10:04 +02:00
Dave Dribin
54d5d65b62 Add support for Nandland Go Board 2021-06-28 09:10:04 +02:00
Gwenhael Goavec-Merou
5e74b13c24 Add support for Terasic DE10 Nano Kit 2021-06-22 17:54:50 +02:00
Olof Kindgren
7f7ea07260 Document memory instructions 2021-06-11 21:48:20 +02:00
Olof Kindgren
a1e5a5ea80 Add timing diagram for interrupts and ecall/ebreak 2021-06-10 23:56:10 +02:00
Olof Kindgren
cae472b29e Document one-stage instructions 2021-06-10 18:15:12 +02:00
Olof Kindgren
c4bf02aeb0 Add instruction life cycle flowchart to doc 2021-06-10 16:52:33 +02:00
Olof Kindgren
c2cdd44f73 Expose and document PRE_REGISTER 2021-06-05 22:56:37 +02:00
Sylvain Munaut
259d5a10ed decode: Add option to pre or post register during decoding 
Either the input from instruction bus is registered and the
outputs are generated combinatorially (PRE_REGISTER mode), or
the input from the instruction bus is decoded combinatorially
and the result of decoding is registered (POST_REGISTER mode).

First is smaller because it allows synthesis to optimize decoding
logic with its users, but is slow. The second one is faster but
slightly bigger.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-05-28 21:26:54 +02:00