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add memlib/fifo_simple_dram + test benches

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- add fifo_simple_dram: simple fifo with CE/WE interface, dram based
- add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2
- add simclkv: test bench clock generator with variable period
This commit is contained in:
wfjm 2019-02-22 19:09:42 +01:00
parent 5a3c40a846
commit 0c395856d7
27 changed files with 2239 additions and 3 deletions
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9
rtl/vlib/memlib/fifo_simple_dram.vbom Normal file
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# libs
../slvtypes.vhd
memlib.vhd
# components
[sim]ram_1swar_gen.vbom
[xst]ram_1swar_gen_unisim.vbom
[vsyn]ram_1swar_gen.vbom
# design
fifo_simple_dram.vhd

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rtl/vlib/memlib/fifo_simple_dram.vhd Normal file
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-- $Id: fifo_simple_dram.vhd 1109 2019-02-09 13:36:41Z mueller $
--
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fifo_simple_dram - syn
-- Description: FIFO, CE/WE interface, distributed RAM based
--
-- Dependencies: ram_1swar_gen
--
-- Test bench: tb/tb_fifo_simple_dram
-- Target Devices: generic Spartan, Artix
-- Tool versions: ise 14.7; viv 2017.2-2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_simple_dram is -- fifo, CE/WE interface, dram based
generic (
AWIDTH : positive := 6; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
);
end fifo_simple_dram;
architecture syn of fifo_simple_dram is
type regs_type is record
waddr : slv(AWIDTH-1 downto 0); -- write address
raddr : slv(AWIDTH-1 downto 0); -- read address
empty : slbit; -- empty flag
full : slbit; -- full flag
end record regs_type;
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RAM_WE : slbit := '0';
signal RAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
RAM : ram_1swar_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
WE => RAM_WE,
ADDR => RAM_ADDR,
DI => DI,
DO => DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CE, WE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iram_we : slbit := '0';
variable iram_addr : slv(AWIDTH-1 downto 0) := (others=>'0');
variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
iram_we := '0';
if WE = '1' then -- select RAM address
iram_addr := r.waddr; -- for write
else
iram_addr := r.raddr; -- for read
end if;
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
if CE = '1' then -- do read or write
if WE = '1' then -- do write
if r.full = '0' then -- only if not full
iram_we := '1'; -- assert write enable
n.waddr := slv(unsigned(r.waddr) + 1); -- advance address
n.empty := '0'; -- can't be empty after write
if unsigned(isize) = memsize-2 then -- check for full
n.full := '1';
end if;
end if;
else -- do read
if r.empty = '0' then -- only if not empty
n.raddr := slv(unsigned(r.raddr) + 1); -- advance address
n.full := '0'; -- can't be full after read
if unsigned(isize) = 1 then -- check for empty
n.empty := '1';
end if;
end if;
end if;
end if;
N_REGS <= n;
RAM_ADDR <= iram_addr;
RAM_WE <= iram_we;
EMPTY <= r.empty;
FULL <= r.full;
SIZE <= isize;
end process proc_next;
-- synthesis translate_off
proc_moni: process (CLK)
variable oline : line;
begin
if rising_edge(CLK) then
if RESET='0' and CE='1' then -- not in reset and active
if WE = '0' then
if R_REGS.empty='1' then -- read on empty fifo
write(oline, now, right, 12);
write(oline, string'(" read on empty fifo - FAIL in "));
write(oline, fifo_simple_dram'path_name);
writeline(output, oline);
end if;
else
if R_REGS.full='1' then -- write on full fifo
write(oline, now, right, 12);
write(oline, string'(" write on full fifo - FAIL in "));
write(oline, fifo_simple_dram'path_name);
writeline(output, oline);
end if;
end if;
end if;
end if;
end process proc_moni;
-- synthesis translate_on
end syn;

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rtl/vlib/memlib/memlib.vhd
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-- $Id: memlib.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: memlib.vhd 1109 2019-02-09 13:36:41Z mueller $
--
-- Copyright 2006-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -17,9 +17,10 @@
-- asynchronus rams; Fifo's.
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-03 1109 1.1.1 add fifo_simple_dram
-- 2016-03-25 751 1.1 add fifo_2c_dram2
-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0.2 change generic default for BRAM models
@ -166,6 +167,23 @@ component ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
);
end component;
component fifo_simple_dram is -- fifo, CE/WE interface, dram based
generic (
AWIDTH : positive := 6; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
);
end component;
component fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
generic (
AWIDTH : positive := 4; -- address width (sets size)

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tb_fifo_1c_dram
tb_fifo_1c_dram_stim
tb_fifo_2c_dram
tb_fifo_2c_dram_stim
tb_fifo_2c_dram2
tb_fifo_2c_dram2_stim
tb_fifo_simple_dram
tb_fifo_simple_dram_stim

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# $Id: Makefile 1109 2019-02-09 13:36:41Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2019-02-09 1109 1.2 add tb_fifo_simple_dram
# 2016-03-25 751 1.1 add tb_fifo_2c_dram2
# 2016-03-13 744 1.0 Initial version
#
EXE_all = tb_fifo_1c_dram
EXE_all = tb_fifo_simple_dram
EXE_all += tb_fifo_2c_dram
EXE_all += tb_fifo_2c_dram2
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
endif
#

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# -*- makefile-gmake -*-
# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2014-07-27 545 1.4.1 make reference board configurable via XTW_BOARD
# 2011-08-13 405 1.4 use includes from rtl/make
# 2009-11-21 252 1.3 add ISim support
# 2007-11-26 98 1.2 use make includes
# 2007-07-06 64 1.1 use vbomconv
# 2007-06-29 61 1.0.1 add clean and all
# 2007-06-06 49 1.0 Initial version
#
EXE_all = tb_fifo_1c_dram
EXE_all += tb_fifo_2c_dram
#
# reference board for test synthesis is Spartan-6 based Nexys3
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
endif
#

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rtl/vlib/memlib/tb/tb_fifo_2c_dram.vbom Normal file
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# libs
../../slvtypes.vhd
../../simlib/simlib.vhd
# components
../../simlib/simclkv.vbom
../../simlib/simclkcnt.vbom
${uut := tbd_fifo_2c_dram.vbom} -UUT
# design
tb_fifo_2c_dram.vhd

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rtl/vlib/memlib/tb/tb_fifo_2c_dram.vhd Normal file
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-- $Id: tb_fifo_2c_dram.vhd 984 2018-01-02 20:56:27Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_fifo_2c_dram - sim
-- Description: Test bench for fifo_2c_dram
--
-- Dependencies: simlib/simclkv
-- simlib/simclkvcnt
-- tbd_fifo_2c_dram [UUT]
--
-- To test: fifo_2c_dram
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.3, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-11-07 421 1.0.5 now numeric_std clean
-- 2010-06-03 299 1.0.4 use sv_ prefix for shared variables
-- 2010-04-17 277 1.0.3 use direct instantiation of tbd_
-- 2009-11-22 252 1.0.2 CLK*_CYCLE now 31 bits
-- 2007-12-28 107 1.0.1 add reset and check handling
-- 2007-12-28 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_fifo_2c_dram is
end tb_fifo_2c_dram;
architecture sim of tb_fifo_2c_dram is
signal CLKW : slbit := '0';
signal CLKR : slbit := '0';
signal RESETW : slbit := '0';
signal RESETR : slbit := '0';
signal DI : slv16 := (others=>'0');
signal ENA : slbit := '0';
signal BUSY : slbit := '0';
signal DO : slv16 := (others=>'0');
signal VAL : slbit := '0';
signal SIZEW : slv4 := (others=>'0');
signal SIZER : slv4 := (others=>'0');
signal N_HOLD : slbit := '0';
signal R_HOLD : slbit := '0';
signal CLKW_PERIOD : Delay_length := 20 ns;
signal CLKR_PERIOD : Delay_length := 20 ns;
signal CLK_HOLD : slbit := '1';
signal CLK_STOP : slbit := '0';
signal CLKW_CYCLE : integer := 0;
signal CLKR_CYCLE : integer := 0;
signal CLKR_C2OUT : Delay_length := 10 ns;
shared variable sv_nrstr : integer := 0;
shared variable sv_ndatar : integer := 0; -- data counter (fifo data output)
begin
CLKWGEN : simclkv
port map (
CLK => CLKW,
CLK_PERIOD => CLKW_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKWCNT : simclkcnt port map (CLK => CLKW, CLK_CYCLE => CLKW_CYCLE);
CLKRGEN : simclkv
port map (
CLK => CLKR,
CLK_PERIOD => CLKR_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKRCNT : simclkcnt port map (CLK => CLKR, CLK_CYCLE => CLKR_CYCLE);
UUT : entity work.tbd_fifo_2c_dram
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => R_HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
proc_stim: process
file fstim : text open read_mode is "tb_fifo_2c_dram_stim";
variable iline : line;
variable oline : line;
variable dname : string(1 to 6) := (others=>' ');
variable ok : boolean;
variable dtime : Delay_length := 0 ns;
variable nwait : integer := 0; --
variable nword : integer := 0; --
variable nbusy : integer := 0; -- number of busy before accept
variable idi : slv16 := (others=>'0');
variable ndataw : integer := 0; -- data counter (fifo data input)
variable iclkw_period : Delay_length := 20 ns;
variable iclkw_setup : Delay_length := 5 ns;
variable iclkr_period : Delay_length := 20 ns;
variable iclkr_c2out : Delay_length := 10 ns;
begin
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".chold" => -- .chold time
write(oline, string'(".chold"));
writeline(output, oline);
read_ea(iline, dtime);
CLK_HOLD <= '1';
wait for dtime;
CLK_HOLD <= '0';
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
when ".cdef " => -- .cdef wper wset rper rout
write(oline, string'(".cdef "));
writeline(output, oline);
read_ea(iline, iclkw_period);
read_ea(iline, iclkw_setup);
read_ea(iline, iclkr_period);
read_ea(iline, iclkr_c2out);
CLKW_PERIOD <= iclkw_period;
CLKR_PERIOD <= iclkr_period;
CLKR_C2OUT <= iclkr_c2out;
if CLK_HOLD = '0' then
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
end if;
when ".ndata" => -- .ndata num
read_ea(iline, ndataw);
sv_ndatar := ndataw;
when ".hold " => -- .hold time
read_ea(iline, dtime);
if dtime > 0 ns then
N_HOLD <= '1', '0' after dtime;
else -- allow hold abort with 0ns
N_HOLD <= '0';
end if;
when ".wait " => -- .wait ncyc
read_ea(iline, nwait);
wait for nwait*iclkw_period;
when "resetw" => -- resetw ncyc
read_ea(iline, nwait);
RESETW <= '1';
wait for nwait*iclkw_period;
RESETW <= '0';
when "resetr" => -- resetr ncyc
read_ea(iline, nwait);
sv_nrstr := nwait;
when "send " => -- send nw nd
read_ea(iline, nwait);
read_ea(iline, nword);
for i in 1 to nword loop
wait for nwait*iclkw_period;
idi := slv(to_unsigned(ndataw, 16));
ndataw := ndataw + 1;
DI <= idi;
ENA <= '1';
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for iclkw_period;
end loop;
writetimestamp(oline, CLKW_CYCLE, ": stim ");
write(oline, idi, right, 18);
write(oline, SIZEW, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(idi)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZEW)), right, 2);
write(oline, string'(")"));
if nbusy > 0 then
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
end if;
writeline(output, oline);
wait for iclkw_period;
ENA <= '0';
end loop; -- i
when others => -- bad directive
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
if N_HOLD = '1' then
wait until N_HOLD='0';
end if;
wait for 20*(iclkw_period+iclkr_period);
CLK_STOP <= '1';
writetimestamp(oline, CLKW_CYCLE, ": DONE-w ");
writeline(output, oline);
writetimestamp(oline, CLKR_CYCLE, ": DONE-r ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable nhold : integer := 0; -- number of hold cycles before accept
variable isizer_last : slv4 := (others=>'0');
variable ido : slv16 := (others=>'0');
begin
loop
wait until rising_edge(CLKR);
wait for CLKR_C2OUT;
if VAL = '1' then
if R_HOLD = '1' then
nhold := nhold + 1;
else
ido := slv(to_unsigned(sv_ndatar, 16));
sv_ndatar := sv_ndatar + 1;
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, DO, right, 18);
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(DO)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
if nhold > 0 then
write(oline, string'(" nhold="));
write(oline, nhold, right, 2);
end if;
if DO = ido then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, ido, right, 18);
end if;
writeline(output, oline);
nhold := 0;
end if;
else
if SIZER /= isizer_last then
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, string'(" "));
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
writeline(output, oline);
end if;
end if;
isizer_last := SIZER;
end loop;
end process proc_moni;
proc_clkr: process (CLKR)
begin
if rising_edge(CLKR) then
R_HOLD <= N_HOLD;
if sv_nrstr > 0 then
RESETR <= '1';
sv_nrstr := sv_nrstr - 1;
else
RESETR <= '0';
end if;
end if;
end process proc_clkr;
end sim;

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rtl/vlib/memlib/tb/tb_fifo_2c_dram2.vbom Normal file
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# libs
../../slvtypes.vhd
../../simlib/simlib.vhd
# components
../../simlib/simclkv.vbom
../../simlib/simclkcnt.vbom
${uut := tbd_fifo_2c_dram2.vbom} -UUT
# design
tb_fifo_2c_dram2.vhd

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rtl/vlib/memlib/tb/tb_fifo_2c_dram2.vhd Normal file
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-- $Id: tb_fifo_2c_dram2.vhd 984 2018-01-02 20:56:27Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_fifo_2c_dram2 - sim
-- Description: Test bench for fifo_2c_dram2
--
-- Dependencies: simlib/simclkv
-- simlib/simclkvcnt
-- tbd_fifo_2c_dram [UUT]
--
-- To test: fifo_2c_dram2
--
-- Target Devices: generic
-- Tool versions: viv 2015.5; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-25 751 1.0 Initial version (derived from tb_fifo_2c_dram)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_fifo_2c_dram2 is
end tb_fifo_2c_dram2;
architecture sim of tb_fifo_2c_dram2 is
signal CLKW : slbit := '0';
signal CLKR : slbit := '0';
signal RESETW : slbit := '0';
signal RESETR : slbit := '0';
signal DI : slv16 := (others=>'0');
signal ENA : slbit := '0';
signal BUSY : slbit := '0';
signal DO : slv16 := (others=>'0');
signal VAL : slbit := '0';
signal SIZEW : slv4 := (others=>'0');
signal SIZER : slv4 := (others=>'0');
signal N_HOLD : slbit := '0';
signal R_HOLD : slbit := '0';
signal CLKW_PERIOD : Delay_length := 20 ns;
signal CLKR_PERIOD : Delay_length := 20 ns;
signal CLK_HOLD : slbit := '1';
signal CLK_STOP : slbit := '0';
signal CLKW_CYCLE : integer := 0;
signal CLKR_CYCLE : integer := 0;
signal CLKR_C2OUT : Delay_length := 10 ns;
shared variable sv_nrstr : integer := 0;
shared variable sv_ndatar : integer := 0; -- data counter (fifo data output)
begin
CLKWGEN : simclkv
port map (
CLK => CLKW,
CLK_PERIOD => CLKW_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKWCNT : simclkcnt port map (CLK => CLKW, CLK_CYCLE => CLKW_CYCLE);
CLKRGEN : simclkv
port map (
CLK => CLKR,
CLK_PERIOD => CLKR_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKRCNT : simclkcnt port map (CLK => CLKR, CLK_CYCLE => CLKR_CYCLE);
UUT : entity work.tbd_fifo_2c_dram2
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => R_HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
proc_stim: process
file fstim : text open read_mode is "tb_fifo_2c_dram2_stim";
variable iline : line;
variable oline : line;
variable dname : string(1 to 6) := (others=>' ');
variable ok : boolean;
variable dtime : Delay_length := 0 ns;
variable nwait : integer := 0; --
variable nword : integer := 0; --
variable nbusy : integer := 0; -- number of busy before accept
variable idi : slv16 := (others=>'0');
variable ndataw : integer := 0; -- data counter (fifo data input)
variable iclkw_period : Delay_length := 20 ns;
variable iclkw_setup : Delay_length := 5 ns;
variable iclkr_period : Delay_length := 20 ns;
variable iclkr_c2out : Delay_length := 10 ns;
begin
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".chold" => -- .chold time
write(oline, string'(".chold"));
writeline(output, oline);
read_ea(iline, dtime);
CLK_HOLD <= '1';
wait for dtime;
CLK_HOLD <= '0';
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
when ".cdef " => -- .cdef wper wset rper rout
write(oline, string'(".cdef "));
writeline(output, oline);
read_ea(iline, iclkw_period);
read_ea(iline, iclkw_setup);
read_ea(iline, iclkr_period);
read_ea(iline, iclkr_c2out);
CLKW_PERIOD <= iclkw_period;
CLKR_PERIOD <= iclkr_period;
CLKR_C2OUT <= iclkr_c2out;
if CLK_HOLD = '0' then
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
end if;
when ".ndata" => -- .ndata num
read_ea(iline, ndataw);
sv_ndatar := ndataw;
when ".hold " => -- .hold time
read_ea(iline, dtime);
if dtime > 0 ns then
N_HOLD <= '1', '0' after dtime;
else -- allow hold abort with 0ns
N_HOLD <= '0';
end if;
when ".wait " => -- .wait ncyc
read_ea(iline, nwait);
wait for nwait*iclkw_period;
when "resetw" => -- resetw ncyc
read_ea(iline, nwait);
RESETW <= '1';
wait for nwait*iclkw_period;
RESETW <= '0';
when "resetr" => -- resetr ncyc
read_ea(iline, nwait);
sv_nrstr := nwait;
when "send " => -- send nw nd
read_ea(iline, nwait);
read_ea(iline, nword);
for i in 1 to nword loop
wait for nwait*iclkw_period;
idi := slv(to_unsigned(ndataw, 16));
ndataw := ndataw + 1;
DI <= idi;
ENA <= '1';
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for iclkw_period;
end loop;
writetimestamp(oline, CLKW_CYCLE, ": stim ");
write(oline, idi, right, 18);
write(oline, SIZEW, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(idi)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZEW)), right, 2);
write(oline, string'(")"));
if nbusy > 0 then
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
end if;
writeline(output, oline);
wait for iclkw_period;
ENA <= '0';
end loop; -- i
when others => -- bad directive
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
if N_HOLD = '1' then
wait until N_HOLD='0';
end if;
wait for 20*(iclkw_period+iclkr_period);
CLK_STOP <= '1';
writetimestamp(oline, CLKW_CYCLE, ": DONE-w ");
writeline(output, oline);
writetimestamp(oline, CLKR_CYCLE, ": DONE-r ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable nhold : integer := 0; -- number of hold cycles before accept
variable isizer_last : slv4 := (others=>'0');
variable ido : slv16 := (others=>'0');
begin
loop
wait until rising_edge(CLKR);
wait for CLKR_C2OUT;
if VAL = '1' then
if R_HOLD = '1' then
nhold := nhold + 1;
else
ido := slv(to_unsigned(sv_ndatar, 16));
sv_ndatar := sv_ndatar + 1;
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, DO, right, 18);
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(DO)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
if nhold > 0 then
write(oline, string'(" nhold="));
write(oline, nhold, right, 2);
end if;
if DO = ido then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, ido, right, 18);
end if;
writeline(output, oline);
nhold := 0;
end if;
else
if SIZER /= isizer_last then
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, string'(" "));
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
writeline(output, oline);
end if;
end if;
isizer_last := SIZER;
end loop;
end process proc_moni;
proc_clkr: process (CLKR)
begin
if rising_edge(CLKR) then
R_HOLD <= N_HOLD;
if sv_nrstr > 0 then
RESETR <= '1';
sv_nrstr := sv_nrstr - 1;
else
RESETR <= '0';
end if;
end if;
end process proc_clkr;
end sim;

6
rtl/vlib/memlib/tb/tb_fifo_2c_dram2_ssim.vbom Normal file
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@ -0,0 +1,6 @@
# configure for _*sim case
# configure
uut = tbd_fifo_2c_dram2_ssim.vhd
# design
tb_fifo_2c_dram2.vbom
@top:tb_fifo_2c_dram2

254
rtl/vlib/memlib/tb/tb_fifo_2c_dram2_stim.dat Normal file
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# $Id: tb_fifo_2c_dram2_stim.dat 751 2016-03-25 19:46:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-25 751 1.0 Initial version (derived from tb_fifo_2c_dram2_stim)
#
C ------------------------------------------------
C setup CLKW=20ns CLKR=23ns
#
.cdef 20 ns 5 ns 23 ns 10 ns
.chold 200 ns
#
C test reset handling
#
.wait 10
resetw 1
.wait 20
resetr 1
.wait 20
#
resetw 5
.wait 20
resetr 5
.wait 20
#
.hold 400 ns
send 0 10
resetw 1
#
.wait 20
#
.hold 400 ns
send 0 10
resetr 1
#
.wait 20
.hold 0 ns
.ndata 0
.wait 20
#
C normal tests
#
send 0 50
send 1 50
.wait 30
# test small holds
send 0 10
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.wait 30
# test long hold (for >32 clkw, so it blocks)
.hold 750 ns
send 1 50
.wait 30
C ------------------------------------------------
C setup CLKW=20ns CLKR=17ns
.cdef 20 ns 5 ns 17 ns 10 ns
# send 50
send 0 50
send 1 50
.wait 30
# test small holds
send 0 10
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.wait 30
# test long hold (for >32 clkw, so it blocks)
.hold 750 ns
send 1 50
.wait 30
C ------------------------------------------------
C setup CLKW=20ns CLKR=53ns
.cdef 20 ns 5 ns 53 ns 10 ns
# send 50
send 0 50
send 1 50
.wait 30
# test small holds
send 0 10
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.wait 30
# test long hold (for >32 clkw, so it blocks)
.hold 750 ns
send 1 50
.wait 30
C ------------------------------------------------
C setup CLKW=50ns CLKR=23ns
.cdef 50 ns 5 ns 23 ns 10 ns
# send 50
send 0 50
send 1 50
.wait 30
# test small holds
send 0 10
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.wait 30
# test long hold (for >32 clkw, so it blocks)
.hold 2000 ns
send 1 50
.wait 60

6
rtl/vlib/memlib/tb/tb_fifo_2c_dram_ssim.vbom Normal file
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@ -0,0 +1,6 @@
# configure for _*sim case
# configure
uut = tbd_fifo_2c_dram_ssim.vhd
# design
tb_fifo_2c_dram.vbom
@top:tb_fifo_2c_dram

254
rtl/vlib/memlib/tb/tb_fifo_2c_dram_stim.dat Normal file
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# $Id: tb_fifo_2c_dram_stim.dat 107 2007-12-30 18:46:47Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2007-12-28 107 1.0.1 add reset tests
# 2007-12-28 106 1.0 Initial version
#
C ------------------------------------------------
C setup CLKW=20ns CLKR=23ns
#
.cdef 20 ns 5 ns 23 ns 10 ns
.chold 200 ns
#
C test reset handling
#
resetw 1
.wait 20
resetr 1
.wait 20
#
resetw 5
.wait 20
resetr 5
.wait 20
#
.hold 400 ns
send 0 10
resetw 1
#
.wait 20
#
.hold 400 ns
send 0 10
resetr 1
#
.wait 20
.hold 0 ns
.ndata 0
.wait 20
#
C normal tests
#
send 0 50
send 1 50
.wait 30
# test small holds
send 0 10
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.wait 30
# test long hold (for >32 clkw, so it blocks)
.hold 750 ns
send 1 50
.wait 30
C ------------------------------------------------
C setup CLKW=20ns CLKR=17ns
.cdef 20 ns 5 ns 17 ns 10 ns
# send 50
send 0 50
send 1 50
.wait 30
# test small holds
send 0 10
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.wait 30
# test long hold (for >32 clkw, so it blocks)
.hold 750 ns
send 1 50
.wait 30
C ------------------------------------------------
C setup CLKW=20ns CLKR=53ns
.cdef 20 ns 5 ns 53 ns 10 ns
# send 50
send 0 50
send 1 50
.wait 30
# test small holds
send 0 10
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.hold 25 ns
send 0 2
.wait 30
# test long hold (for >32 clkw, so it blocks)
.hold 750 ns
send 1 50
.wait 30
C ------------------------------------------------
C setup CLKW=50ns CLKR=23ns
.cdef 50 ns 5 ns 23 ns 10 ns
# send 50
send 0 50
send 1 50
.wait 30
# test small holds
send 0 10
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.hold 75 ns
send 0 2
.wait 30
# test long hold (for >32 clkw, so it blocks)
.hold 2000 ns
send 1 50
.wait 60

9
rtl/vlib/memlib/tb/tb_fifo_simple_dram.vbom Normal file
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@ -0,0 +1,9 @@
# libs
../../slvtypes.vhd
../../simlib/simlib.vhd
# components
../../simlib/simclk.vbom
../../simlib/simclkcnt.vbom
${uut := tbd_fifo_simple_dram.vbom} -UUT
# design
tb_fifo_simple_dram.vhd

257
rtl/vlib/memlib/tb/tb_fifo_simple_dram.vhd Normal file
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-- $Id: tb_fifo_simple_dram.vhd 1109 2019-02-09 13:36:41Z mueller $
--
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_fifo_simple_dram - sim
-- Description: Test bench for fifo_simple_dram
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_fifo_simple_dram [UUT]
--
-- To test: fifo_simple_dram
--
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2017.2 ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_fifo_simple_dram is
end tb_fifo_simple_dram;
architecture sim of tb_fifo_simple_dram is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE : slbit := '0';
signal WE : slbit := '0';
signal DI : slv16 := (others=>'0');
signal DO : slv16 := (others=>'0');
signal EMPTY : slbit := '0';
signal FULL : slbit := '0';
signal SIZE : slv4 := (others=>'0');
signal N_EMPTY : slbit := '1';
signal N_FULL : slbit := '0';
signal N_SIZE : slv4 := (others=>'0');
signal R_EMPTY : slbit := '1';
signal R_FULL : slbit := '0';
signal R_SIZE : slv4 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_fifo_simple_dram
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
WE => WE,
DI => DI,
DO => DO,
EMPTY => EMPTY,
FULL => FULL,
SIZE => SIZE
);
proc_stim: process
file fstim : text open read_mode is "tb_fifo_simple_dram_stim";
variable iline : line;
variable oline : line;
variable dname : string(1 to 6) := (others=>' ');
variable ok : boolean;
variable nwait : integer := 0; --
variable idi : slv16 := (others=>'0');
variable ido : slv16 := (others=>'0');
variable isize : slv4 := (others=>'0');
begin
wait for clock_offset;
wait until rising_edge(CLK);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".wait " => -- .wait ncyc
read_ea(iline, nwait);
for i in 1 to nwait loop
wait until rising_edge(CLK);
end loop; -- i
when "reset " => -- reset
writetimestamp(oline, CLK_CYCLE, ": reset");
writeline(output, oline);
RESET <= '1';
isize := "0000";
N_EMPTY <= '1';
N_FULL <= '0';
N_SIZE <= isize;
wait until rising_edge(CLK);
RESET <= '0';
wait for 0 ns;
when "write " => -- write di
readgen_ea(iline, idi, 16);
writetimestamp(oline, CLK_CYCLE, ": write");
write(oline, idi, right, 18);
writeline(output, oline);
CE <= '1';
WE <= '1';
DI <= idi;
isize := slv(unsigned(isize) + 1);
N_SIZE <= isize;
N_EMPTY <= '0';
if isize = "1111" then
N_FULL <= '1';
end if;
wait until rising_edge(CLK);
CE <= '0';
WE <= '0';
wait for 0 ns;
when "read " => -- read do
readgen_ea(iline, ido, 16);
CE <= '1';
WE <= '0';
isize := slv(unsigned(isize) - 1);
N_SIZE <= isize;
N_FULL <= '0';
if isize = "0000" then
N_EMPTY <= '1';
end if;
wait for c2out_time; -- check same cycle read response
writetimestamp(oline, CLK_CYCLE, ": read ");
write(oline, DO, right, 18);
if DO = ido then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, ido, right, 18);
end if;
writeline(output, oline);
wait until rising_edge(CLK);
CE <= '0';
wait for 0 ns;
when others => -- bad directive
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
end loop; -- file_loop:
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 20*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable iempty_1 : slbit := '1';
begin
loop
wait until rising_edge(CLK); -- at rising clock
R_EMPTY <= N_EMPTY; -- latch expected values
R_FULL <= N_FULL;
R_SIZE <= N_SIZE;
wait for c2out_time; -- after clock2output time check
if EMPTY='0' or iempty_1 ='0' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, DO, right, 18);
write(oline, EMPTY, right, 3);
write(oline, FULL, right, 2);
write(oline, SIZE, right, 6);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(SIZE)), right, 2);
write(oline, string'(")"));
if EMPTY /= R_EMPTY then
write(oline, string'(" FAIL EMPTY exp="));
write(oline, R_EMPTY);
end if;
if FULL /= R_FULL then
write(oline, string'(" FAIL FULL exp="));
write(oline, R_FULL);
end if;
if SIZE /= R_SIZE then
write(oline, string'(" FAIL SIZE exp="));
write(oline, R_SIZE);
end if;
writeline(output, oline);
end if;
iempty_1 := EMPTY;
end loop;
end process proc_moni;
end sim;

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# $Id: tb_fifo_simple_dram_stim.dat 1109 2019-02-09 13:36:41Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2019-02-09 1109 1.0 Initial version
#
C ------------------------------------------------
C single write-read
#
.wait 10
write 0101
read 0101
write 0102
read 0102
write 0103
read 0103
#
C paired write-read
#
.wait 5
write 0201
write 0202
read 0201
read 0202
#
C write-reset-write-read
#
.wait 5
write 0301
write 0302
write 0303
reset
write 0304
read 0304
#
C write till full
write 0401
write 0402
write 0403
write 0404
write 0405
write 0406
write 0407
write 0408
write 0409
write 040a
write 040b
write 040c
write 040d
write 040e
write 040f
.wait 5
#
read 0401
read 0402
read 0403
read 0404
#
write 0501
write 0502
write 0503
write 0504
#
read 0405
read 0406
read 0407
read 0408
read 0409
read 040a
read 040b
read 040c
read 040d
read 040e
read 040f
read 0501
read 0502
read 0503
read 0504

7
rtl/vlib/memlib/tb/tbd_fifo_2c_dram.vbom Normal file
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# libs
../../slvtypes.vhd
../memlib.vhd
# components
../fifo_2c_dram.vbom
# design
tbd_fifo_2c_dram.vhd

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-- $Id: tbd_fifo_2c_dram.vhd 984 2018-01-02 20:56:27Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_fifo_2c_dram - syn
-- Description: Wrapper for fifo_2c_dram to avoid records & generics. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: fifo_2c_dram
--
-- To test: fifo_2c_dram
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-04-24 281 11.4 L68 xc3s1000-4 36 43 32 52 s 8.34
--
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-28 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity tbd_fifo_2c_dram is -- fifo, 2 clock, dram based [tb design]
-- generic: AWIDTH=4; DWIDTH=16
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- reset (synchronous with CLKW)
RESETR : in slbit; -- reset (synchronous with CLKR)
DI : in slv16; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZEW : out slv4; -- number slots to write (synch w/ CLKW)
SIZER : out slv4 -- number slots to read (synch w/ CLKR)
);
end tbd_fifo_2c_dram;
architecture syn of tbd_fifo_2c_dram is
begin
FIFO : fifo_2c_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
end syn;

7
rtl/vlib/memlib/tb/tbd_fifo_2c_dram2.vbom Normal file
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# libs
../../slvtypes.vhd
../memlib.vhd
# components
../fifo_2c_dram2.vbom
# design
tbd_fifo_2c_dram2.vhd

80
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-- $Id: tbd_fifo_2c_dram2.vhd 984 2018-01-02 20:56:27Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_fifo_2c_dram2 - syn
-- Description: Wrapper for fifo_2c_dram2 to avoid records & generics. It
-- has a port interface which will not be modified by synthesis
-- (no records, no generic port).
--
-- Dependencies: fifo_2c_dram2
--
-- To test: fifo_2c_dram2
--
-- Target Devices: generic
--
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-28 106 1.0 Initial version (tbd_fifo_2c_dram2)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity tbd_fifo_2c_dram2 is -- fifo, 2 clock, dram based [tb design]
-- generic: AWIDTH=4; DWIDTH=16
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- reset (synchronous with CLKW)
RESETR : in slbit; -- reset (synchronous with CLKR)
DI : in slv16; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZEW : out slv4; -- number slots to write (synch w/ CLKW)
SIZER : out slv4 -- number slots to read (synch w/ CLKR)
);
end tbd_fifo_2c_dram2;
architecture syn of tbd_fifo_2c_dram2 is
begin
FIFO : fifo_2c_dram2
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
end syn;

7
rtl/vlib/memlib/tb/tbd_fifo_simple_dram.vbom Normal file
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# libs
../../slvtypes.vhd
../memlib.vhd
# components
../fifo_simple_dram.vbom
# design
tbd_fifo_simple_dram.vhd

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-- $Id: tbd_fifo_simple_dram.vhd 1109 2019-02-09 13:36:41Z mueller $
--
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_fifo_simple_dram - syn
-- Description: Wrapper for fifo_simple_dram to avoid records & generics. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: fifo_simple_dram
--
-- To test: fifo_simple_dram
--
-- Target Devices: generic
--
-- Tool versions: xst 14.7; viv 2017.2; ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity tbd_fifo_simple_dram is -- fifo, CE/WE, dram based [tb design]
-- generic: AWIDTH=4; DWIDTH=16
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv16; -- input data
DO : out slv16; -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv4 -- number of used slots
);
end tbd_fifo_simple_dram;
architecture syn of tbd_fifo_simple_dram is
begin
FIFO : fifo_simple_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
WE => WE,
DI => DI,
DO => DO,
EMPTY => EMPTY,
FULL => FULL,
SIZE => SIZE
);
end syn;

21
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# $Id: tbrun.yml 1109 2019-02-09 13:36:41Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2019-02-01 1109 1.1 Add tb_fifo_simple_dram
# 2016-08-12 797 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, memlib, fifo_simple_dram]
test: |
tbrun_tbw tb_fifo_simple_dram${ms}
- tag: [default, viv, memlib, fifo_2c_dram]
test: |
tbrun_tbw tb_fifo_2c_dram${ms}
- tag: [default, viv, memlib, fifo_2c_dram2]
test: |
tbrun_tbw tb_fifo_2c_dram2${ms}

5
rtl/vlib/simlib/simclkv.vbom Normal file
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# libs
../slvtypes.vhd
# components
# design
simclkv.vhd

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-- $Id: simclkv.vhd 984 2018-01-02 20:56:27Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simclkv - sim
-- Description: Clock generator for test benches, variable period
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 2.0.1 CLK_STOP,CLK_HOLD now optional ports
-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
-- 2011-11-21 432 1.0.2 now numeric_std clean
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-12-27 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity simclkv is -- test bench clock generator
-- with variable period
port (
CLK : out slbit; -- clock
CLK_PERIOD : in Delay_length; -- clock period
CLK_HOLD : in slbit := '0'; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end entity simclkv;
architecture sim of simclkv is
begin
clk_proc: process
variable half_period : Delay_length := 0 ns;
begin
CLK <= '0';
clk_loop: loop
if CLK_HOLD = '1' then
wait until CLK_HOLD='0';
end if;
half_period := CLK_PERIOD/2;
CLK <= '1';
wait for half_period;
CLK <= '0';
wait for CLK_PERIOD-half_period;
exit clk_loop when CLK_STOP = '1';
end loop;
CLK <= '1'; -- final clock cycle for clk_sim
wait for CLK_PERIOD/2;
CLK <= '0';
wait for CLK_PERIOD-CLK_PERIOD/2;
wait; -- endless wait, simulator will stop
end process;
end sim;

1
tbrun.yml
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@ -5,6 +5,7 @@
# 2018-12-30 1099 1.0.1 add tst_mig, bplib/mig
# 2016-08-27 802 1.0 Initial version
#
- include: rtl/vlib/memlib/tb/tbrun.yml
- include: rtl/vlib/comlib/tb/tbrun.yml
- include: rtl/vlib/serport/tb/tbrun.yml
- include: rtl/vlib/rlink/tb/tbrun.yml