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13 Commits

Author SHA1 Message Date
wfjm
76bb350d97 add vlib/xlib/bufg_unisim, encapulate unisim BUFG 2022-07-06 09:34:15 +02:00
wfjm
d3cce101a7 SPDX: rtl/*/*.vhd 2019-07-12 19:01:49 +02:00
wfjm
14362b2a56 Add basic DDR memory support 
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
 2018-12-31 10:00:14 +01:00
wfjm
22bb8e011c reorganize dcm/mmcm/ppl sim models 
- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
 2018-11-09 17:48:56 +01:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
Walter F.J. Mueller
2b5cfb7d96 - Code base cleaned-up for vivado, fsm now inferred 
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
 2016-06-26 16:02:42 +00:00
Walter F.J. Mueller
e91847f8db - added support for Vivado 
- added support for Nexys4 and Basys3 boards
- added RL11 disk support
- lots of documentation updated
 2015-03-09 19:26:25 +00:00
Walter F.J. Mueller
4732555297 - interim release w11a_V0.581 (untagged) 
- new reference system
  - switched from ISE 13.3 to 14.7.
  - map/par behaviour changed, unfortunately unfavorably for w11a. 
    On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can 
    be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
 2014-05-29 21:30:01 +00:00
Walter F.J. Mueller
f2d0f39621 - interim release w11a_V0.54 (untagged) 
- add Nexys3 port of w11a
 2011-12-04 21:25:09 +00:00
Walter F.J. Mueller
3f455d5236 - interim release w11a_V0.532 (untagged) 
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
 2011-11-20 12:31:43 +00:00
Walter F.J. Mueller
e15295649e - interim release w11a_V0.531 (untagged) 
- many small changes to prepare upcoming support for Spartan-6 and
  usage of Cypress FX2 USB interface on nexys2/3 and atlys boards
 2011-09-12 20:52:31 +00:00
Walter F.J. Mueller
16ce5b2091 - interim release w11a_V0.51 (untagged) 
- migrate to ibus protocol verion 2
  - nexys2 systems now with DCM derived system clock supported
  - sys_w11a_n2 now runs with 58 MHz clksys
 2010-11-27 23:17:50 +00:00
Walter F.J. Mueller
3335c61549 initial source upload (no docs yet) 2010-07-09 18:14:38 +00:00